Memory instantiation - help needed

[vivek_p]

I have two identical units in my design

I have designed a module "design.v"

I have also created two instances of design d1 and d2.

design d1 (ports lists);
design d2 (port lists);

design contains instantiation of lot of sub-modules and a memory module.

But in design d1 and d2 the memory module should be initialized with different values (Memory architecture is the same).
All other modules are the same.

How can I do the initialisation withour renaming the blocks and making two copies

design1 d1(ports lists); // renaming the blocks
design1 d2(port lists);

Can anyone help me in solving this issue..........

 

[entropy]

Once again, synthesis has nothing to do with memory initialization.

Just complie them. In your testbench, use readmemb to initialize your memory values with hierarchical names...

 

[mux_master]

I agree this won't have anything to do with synthesis. You can load it in the test bench. If you want to load it in the actual module for some reason you can do it by passing a parameter. Here is the parameter syntax in case you are not familiar.
**broken link removed**