Memory initialisation with $readmemb command

Status
Not open for further replies.
V

vivek_p

Advanced Member level 4
Joined
Feb 16, 2010
Messages
115
Helped
10
Reputation
24
Reaction score
9
Trophy points
1,298
Activity points
2,009
$readmemb

In my design I am using 2 read- 1 write port RAM. I have initialized the memory with contents using $readmemb (using a .dat file).....Simulation works fine. But there is a problem with synthesis. It is showing error. Please help.

Is there any other better way to initialise memory so that we can easily load the data mem contents.................
 

Re: $readmemb

If you know the hierarchical path to the memory storage array to your memory model, you can write a simple verilog routines like the following to use in initializing your memory.

task write_mem_backdoor;
input [13:0] addr;
input [23:0] data;
begin
dut.eGigatron.egig_prcsr.ltl_tb_u0.inst.memory[addr] = data;
end
endtask

task read_mem_backdoor;
input [13:0] addr;
output[23:0] data;
begin
data = dut.eGigatron.egig_prcsr.ltl_tb_u0.inst.memory[addr];
end
endtask

initial begin
for (i = 0; i < 14'h3fff; i = i + 1) begin
write_mem_backdoor(i, 0); // initial all mem locations to 0
end
end
 

Can you please explain it in detail.................

What will be the hardware equivalent of 'for' loop?
 

These should be part of your testbench, not your design.

- Hung
 

    V

    vivek_p

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…