Memory Design Help Verilog

I'm quite new to verilog and don't quite understand things that well yet so I apologize if this is a simple question but I'm having a difficult time putting my design into verilog. It's a 64x8 Memory Unit that's suppose to be designed with a 16x4 SRAM. I think I have the decoder module and 16x4 but not sure how to do the 64x8. These are the only three modules I'll need correct?


16x4 SRAM:


2 to 4 Decoder:



I'm clueless at this point and I've looked and couldn't find any examples of this. I usually could do it if there's some sort of guideline or examples but couldn't find any so I'm unsure what to do as I'm really confused with verilog.

Hi

64X8 means 64 depth and each memory is 8-bit ..

so you have 16X4 memory which means 16 depth and 4-bit ..

first you need to make 16X8 , which will be concatenate two 16X4 memory.

then you can have 4 instance of above (16X8) memory . ..

So total you will have to use 8 instance of 16X4 ..

Let me know if this help or not ..

rahul.achates said:

Hi

64X8 means 64 depth and each memory is 8-bit ..

so you have 16X4 memory which means 16 depth and 4-bit ..

first you need to make 16X8 , which will be concatenate two 16X4 memory.

then you can have 4 instance of above (16X8) memory . ..

So total you will have to use 8 instance of 16X4 ..

Let me know if this help or not ..

Click to expand...

Yes you're right I have that design of what you said. There are two columns of 16x4 on my design. It uses a 2-4 Decoder with 8 units of the 16x4, I guess I don't really understand how to code that into verilog.

well .. you can use a4 and a5 .. to select one block of memory (which would be two 16x4 memory)

something like that --


B0..B1

B2..B3

B4..B5

B6..B7


now for block B0 and B1 , you can use {a4,a5} ==2'b00 ;
for B2..B3 , you can use {a4 ,a5} = 2'b01 ; .. and so on

Rahul

rahul.achates said:

well .. you can use a4 and a5 .. to select one block of memory (which would be two 16x4 memory)

something like that --


B0..B1

B2..B3

B4..B5

B6..B7


now for block B0 and B1 , you can use {a4,a5} ==2'b00 ;
for B2..B3 , you can use {a4 ,a5} = 2'b01 ; .. and so on

Rahul

Click to expand...

Ok I kinda understand it a bit more now, it's getting there. Do you have any sort of skeleton of how the 64x8 memory unit module should look like?

Would I use an always block in the verilog? I mostly need help setting it up

you need to instantiate the 16X4 RAM. No need to use always block.


ram16X4 B0 ( ..
..
..
);

ram16X4 B1 ( ..
..
..
);

ram16X4 B2 ( ..
..
..
);

and so on ..

there is one port in ram16x4 module called chip_en ,

so you can have chip_en_b0 , chip_en_b1 , chip_en_b2 , chip_en_b3 , so on ..

assign chip_en_b0 = _ce0 ;
assign chip_en_b0 = _ce0;
assign chip_en_b1 = _ce1;
assign chip_en_b2 = _ce1;
and so on ..

Hope this should be good enough to code this module ..

Rahul