Memory Banks

Assuming this is dual-port memory, just tie all your input data lines and enables together so it will look like one write port. Obviously, you have to have separate read ports.

But, I have to ask, if you're writing the exact same data to multiple memories, what's the point? No matter which memory you read, it will be the same, right?

barry said:

Assuming this is dual-port memory, just tie all your input data lines and enables together so it will look like one write port. Obviously, you have to have separate read ports.

But, I have to ask, if you're writing the exact same data to multiple memories, what's the point? No matter which memory you read, it will be the same, right?

Click to expand...

Thanks for your reply.The data is not same. They are different data. For example of if I have 20 data, instead of writing serially into memory, I am thinking of dividing the memory into banks and writing and reading them parallely. For example 4 memory banks for 20 data,5 data parallely written in each.So latency can be reduced.

Draw a picture. Are you saying you want to write 20 bits as 5 bit chunks into 4 5-bit wide memories? Why is that any different than writing 20 bits into a single 20-bit wide memory?

barry said:

Draw a picture. Are you saying you want to write 20 bits as 5 bit chunks into 4 5-bit wide memories? Why is that any different than writing 20 bits into a single 20-bit wide memory?

Click to expand...

If i have data in 20 address locations, I would need to write data from it parallely into memory banks like below.

It still is unclear.

The sketch shows one address line and one data line per RAM.
Usually one has address lines to access 2^n different locations.

And usually a RAM has a counterpart to communicate with. A microcontroller an memory controller or it may be some FPGA internal logic.
In either case it should have a defined address bus, data bus, control signals.

What you call RAM seems to be a single data flip flop. Is this the case?

Please give more details about your real application... not some fictive example.

Klaus

LakshmiJL said:

If i have data in 20 address locations, I would need to write data from it parallely into memory banks like below.

Click to expand...

Means that the source ("20 address locations") can't be FPGA block RAM, because block RAM has maximal two ports that can be operated simultaneously.

LakshmiJL said:

If i have data in 20 address locations, I would need to write data from it parallely into memory banks like below.

Click to expand...

so now you are writing 20 different data to twenty different locations?

I think you need to step back and think about what you really are trying to do, because you’ve got everybody here totally confused.

It sounds as though you require a custom array of memory cells. A shift register (rather two identical shift registers) can do the job. They can be made of D flip-flops suggested in post #6. Conceivably you can make it parallel in parallel out. No need to address RAM locations individually.

I guess I used the term shift register loosely. It's up to you how to weigh latency versus ease of assembly. Conceivably shifting data is not necessary.

A bunch of sample-and-holds can also do the job, if you access each data while it holds its value.