Memory Banks

[LakshmiJL]

I need to divide a memory into multiple memory banks(more than 2) and write data to each of the memory bank simultaneously. In this case how is the write and read operation managed. Should I have same number of read and write ports as that of the memory bank?Thanks in advance

 

[barry]

Assuming this is dual-port memory, just tie all your input data lines and enables together so it will look like one write port. Obviously, you have to have separate read ports.

But, I have to ask, if you're writing the exact same data to multiple memories, what's the point? No matter which memory you read, it will be the same, right?

 

[LakshmiJL]

Assuming this is dual-port memory, just tie all your input data lines and enables together so it will look like one write port. Obviously, you have to have separate read ports.

But, I have to ask, if you're writing the exact same data to multiple memories, what's the point? No matter which memory you read, it will be the same, right?

Thanks for your reply.The data is not same. They are different data. For example of if I have 20 data, instead of writing serially into memory, I am thinking of dividing the memory into banks and writing and reading them parallely. For example 4 memory banks for 20 data,5 data parallely written in each.So latency can be reduced.

 

[barry]

Draw a picture. Are you saying you want to write 20 bits as 5 bit chunks into 4 5-bit wide memories? Why is that any different than writing 20 bits into a single 20-bit wide memory?

 

[LakshmiJL]

Draw a picture. Are you saying you want to write 20 bits as 5 bit chunks into 4 5-bit wide memories? Why is that any different than writing 20 bits into a single 20-bit wide memory?

If i have data in 20 address locations, I would need to write data from it parallely into memory banks like below.

 

[KlausST]

It still is unclear.

The sketch shows one address line and one data line per RAM.
Usually one has address lines to access 2^n different locations.

And usually a RAM has a counterpart to communicate with. A microcontroller an memory controller or it may be some FPGA internal logic.
In either case it should have a defined address bus, data bus, control signals.

What you call RAM seems to be a single data flip flop. Is this the case?

Please give more details about your real application... not some fictive example.

Klaus

 

[FvM]

If i have data in 20 address locations, I would need to write data from it parallely into memory banks like below.

Means that the source ("20 address locations") can't be FPGA block RAM, because block RAM has maximal two ports that be operated simultaneously.