Memory access two times problem

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MSAKARIM

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In VHDL code
I have memory i call data from it to change some of it and back it to the same memory again
How can I back it to the same memory with its primary address again ?
 

Your request doesnt make sense - you can just write the data back to the same location you read it from?
 

MSAKARIM said:
In VHDL code
I have memory i call data from it to change some of it and back it to the same memory again
How can I back it to the same memory with its primary address again ?
Click to expand...

What do you mean by back it to the same memory with primary address?? The above statement reading and writing in to the same memory location is possible.
 

sreevenkjan said:
What do you mean by back it to the same memory with primary address?? The above statement reading and writing in to the same memory location is possible.
Click to expand...

i know it is possible but how can i do this (writing data after modification to its location) in VHDL
 

You just do a write cycle when you want to write it.
Why not show us the VHDL you're having trouble with
 
TrickyDicky said:
You just do a write cycle when you want to write it.
Why not show us the VHDL you're having trouble with
Click to expand...

Ok, this my codes
the First : is a memory initialized from file 

Code VHDL - [expand]
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entity inst_memory is
port
(clk,rst: in bit;
inst: OUT bit_VECTOR(7 downto 0));
end inst_memory;
 
architecture behavioral of inst_memory is
   
component LFSR port (
      clk           :in  bit;                    
      reset         :in  bit;                    
      lfsr_out      :out bit_vector (12 downto 0));  end component;
      signal addr:bit_VECTOR(12 downto 0):="0000000000000";
   
  
   -----------
type rom_type is array (0 to 65535) of  integer range 0 to 190;
 
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE romfile : text open read_mode is romfileName; 
variable RomFileLine : line;
variable rom : rom_type;
begin 
for i in 0 to 5086 loop
readline(romfile, RomFileLine);
read(RomFileLine, rom(i));
end loop;
return rom;
end function;
 
signal rom : rom_type := InitRomFromFile("\Users\hp\Documents\Desktop\img.txt");
 
begin
M1: LFSR port map (clk,rst,addr);
inst <= bit_vector(to_unsigned(rom(to_integer(unsigned(addr))),8));
 
end behavioral;
__________________
the second is embbeing module
entity Embedding_Module is
    port(clk,rst:in bit;
         datain :in bit_vector (127 downto 0);
         PixelOut:out integer range 0 to 190);
    end Embedding_Module;
    
    architecture stg of Embedding_module is
        
       
      component inst_memory port(clk,rst : in bit;
           inst: OUT bit_VECTOR(7 downto 0));end component; 
   
       
        signal PixelIn,pixel :bit_vector(7 downto 0);
        
        begin
            G1:inst_memory port map(clk,rst,PixelIn);
            
           PROCESS 
 VARIABLE temp : INTEGER RANGE 0 TO 128;
 BEGIN
 WAIT UNTIL (clk'EVENT AND clk='1');
 temp := temp + 1;
 IF (temp=128) THEN temp := 0;
 END IF;
        
         Pixel<= PixelIn( 7 downto 1) & datain(temp);
         PixelOut<=to_integer(unsigned(pixel));
    END PROCESS;
         
    end stg;


I need to store Pixlout to the memory
 
Last edited by a moderator:

Why is your "memory" defined as a ROM if you plan on updating it with new data?

Because you have it defined as a ROM and you don't have a write port there is no way to put PixelOut into the memory array. Change your design to use a RAM with both read and write ports (simple dual port) or a single read/write port (single port ram).
 

what about this 

Code VHDL - [expand]
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entity inst_memory is
port
(clk,rst,read,write: in bit;
datain :in bit_vector (127 downto 0);
inst: OUT bit_VECTOR(7 downto 0));
end inst_memory;
 
architecture behavioral of inst_memory is
   
component LFSR port (
      clk           :in  bit;                    
      reset         :in  bit;                    
      lfsr_out      :out bit_vector (12 downto 0));  end component;
      signal addr:bit_VECTOR(12 downto 0):="0000000000000";
   
   -------------
   component Embedding_Module port(clk,rst:in bit;
         datain :in bit_vector (127 downto 0);
         PixelOut:out integer range 0 to 190);end component;
   -----------
type rom_type is array (0 to 65535) of  integer range 0 to 190;
 
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE romfile : text open read_mode is romfileName; 
variable RomFileLine : line;
variable rom : rom_type;
begin 
for i in 0 to 5086 loop
readline(romfile, RomFileLine);
read(RomFileLine, rom(i));
end loop;
return rom;
end function;
 
signal pixelout: integer range 0 to 190;
signal rom : rom_type := InitRomFromFile("\Users\hp\Documents\Desktop\img.txt");
 
begin
M1: LFSR port map (clk,rst,addr);
M2:Embedding_Module port map(clk,rst,datain,PixelOut);
red:process(clk,read)
    begin
IF(CLK'EVENT AND CLK='1') THEN 
if(write = '0')then
        IF(read ='1') THEN
inst <= bit_vector(to_unsigned(rom(to_integer(unsigned(addr))),8));
end if ;
end if;
end if;
end process;
 
writ:process(clk,pixelin,write)
begin
IF(CLK'EVENT AND CLK='1') THEN 
if(read = '0') then
        IF(write ='1') THEN
rom(to_integer(unsigned(addr)))<=pixelout;
end if ;
end if;
end if;
end process;
end behavioral;
but i have this error ".vhd(39): Prefix of indexed name must be an array."
 
Last edited by a moderator:

Need help in VHDL code

What is the wrong in this code ,writing process not performed ,can any one help me please 
Code VHDL - [expand]
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entity inst_memory is
port
(clk,rst,read1,write: in bit;
datain :in bit_vector (127 downto 0));
end inst_memory;
------------------------------------------------architecture---------------------
architecture behavioral of inst_memory is
                 --components---
component LFSR port (
      clk           :in  bit;                    
      reset         :in  bit;                    
      lfsr_out      :out bit_vector (12 downto 0));  end component;
 
component Embeding_Module 
    port(clk,rst:in bit;
         PixelIn :in bit_vector(7 downto 0);
         datain :in bit_vector(127 downto 0);
         PixelOut:out integer range 0 to 190);end component;
      
     -----signals-------
      signal addr:bit_VECTOR(12 downto 0):="0000000000000";
   
   signal inst : bit_vector ( 7 downto 0);
  
   signal pixelout: integer range 0 to 190;
type rom_type is array (0 to 65535) of  integer range 0 to 190;
 
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE romfile : text open read_mode is romfileName; 
variable RomFileLine : line;
variable rom : rom_type;
begin 
for i in 0 to 65535 loop
readline(romfile, RomFileLine);
read(RomFileLine, rom(i));
end loop;
return rom;
end function;
signal rom : rom_type := InitRomFromFile("\Users\hp\Documents\Desktop\img.txt");
 
begin
M1: LFSR port map (clk,rst,addr);
M2:Embeding_Module port map (clk,rst,inst,datain,pixelout);
  
---read process
red:process(clk,read1)
    begin
IF(CLK'EVENT AND CLK='1') THEN 
if(write = '0')then
        IF(read1 ='1') THEN
inst <= bit_vector(to_unsigned(rom(to_integer(unsigned(addr))),8));
end if ;
end if;
end if;
end process;
     
----write process
writ:process(clk,write)
begin
IF(CLK'EVENT AND CLK='1') THEN 
if(read1 = '0') then
        IF(write ='1') THEN
rom(to_integer(unsigned(addr)))<=pixelout;
end if ;
end if;
end if;
end process;
end behavioral;
 
Last edited by a moderator:

Re: Need help in VHDL code

line 51 (as posted) has "add r" instead of "addr

I dont really understand your question - this code will do what you tell it to - maybe your testbench is wrong?
 
Re: Need help in VHDL code

TrickyDicky said:
line 51 (as posted) has "add r" instead of "addr

I dont really understand your question - this code will do what you tell it to - maybe your testbench is wrong?
Click to expand...

ok, thanks

but while writing data to another file > not expected values of data stored in the file

this is final code 
Code VHDL - [expand]
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entity ram is
port
(clk,rst,read1,write1: in bit;
datain :in bit_vector (127 downto 0));
end ram;
------------------------------------------------architecture---------------------
architecture behavioral of ram is
                 --components---
component LFSR port (
      clk           :in  bit;                    
      reset         :in  bit;                    
      lfsr_out      :out bit_vector (12 downto 0));  end component;
 
component Embedding_Module 
    port(clk,rst:in bit;
         PixelIn :in bit_vector(7 downto 0);
         datain :in bit_vector(127 downto 0);
         PixelOut:out integer range 0 to 190);end component;
      
     -----signals-------
      signal addr:bit_VECTOR(12 downto 0);
   
   signal inst : bit_vector ( 7 downto 0);
  
   signal pixelout: integer range 0 to 190;
   
type rom_type is array (0 to 65535) of  integer ;
 
impure function InitRomFromFile (RomFileName : in string) return rom_type is
FILE romfile : text open read_mode is romfileName; 
variable RomFileLine : line;
variable rom : rom_type;
begin 
for i in 0 to 65535 loop
readline(romfile, RomFileLine);
read(RomFileLine, rom(i));
end loop;
return rom;
end function;
signal rom : rom_type := InitRomFromFile("D:\Crypto\Just Paper\Codes\XillinxSimulation\stego1\img.txt");
 
begin
M1: LFSR port map (clk,rst,addr);
M2:Embedding_Module port map (clk,rst,inst,datain,pixelout);
  
---read process
red:process(clk,read1)
    begin
IF(CLK'EVENT AND CLK='1') THEN 
if(write1 = '0')then
        IF(read1 ='1') THEN
inst <= bit_vector(to_unsigned(rom(to_integer(unsigned(addr))),8));
end if ;
end if;
end if;
end process;
     
----write process
writ:process(clk,write1)
 
file outfile  : TEXT open WRITE_MODE is "C:\Users\hp\Documents\Desktop\im.txt"; 
   variable    datatosave : integer;
   variable    linenumber : integer:=1; 
   variable endoffile : bit:='0'; 
   variable  outline  : line;  
begin
IF(CLK'EVENT AND CLK='1') THEN 
if(read1 = '0') then
        IF(write1 ='1') THEN
rom(to_integer(unsigned(addr)))<=pixelout;
 
datatosave:=rom(to_integer(unsigned(addr)));
 
 
if(endoffile='0') then   
 
 
write(outline, datatosave);
 
writeline(outfile, outline);
linenumber := linenumber + 1;
else
null;
 
end if;
end if ;
end if;
end if;
end process;
end behavioral;
 
Last edited by a moderator:

if the data in the file is wrong, there is probably a problem you'll probably need to inspect from the waveform.
What is thr problem with the data?
 
What is your end goal here, something that is synthesizable that can be used in an FPGA project or a simulation model of a RAM that you can seed with initial values?

If you need to seed the RAM with initial values there are easier ways to do this. The easy way in Verilog is to load the RAM from a file in an initial block, I'm sure there's some verbose equivalent in VHDL.

Your current code may be good for simulation, but I doubt it will give you meaningful synthesis results.
 

TrickyDicky said:
if the data in the file is wrong, there is probably a problem you'll probably need to inspect from the waveform.
What is thr problem with the data?
Click to expand...

my goal to change only one bit from data and store it again to the memory ,then write it to another text file
data should be slightly different not completely different
by the way data represent pixel's values of a certain image

- - - Updated - - -



I know , I need it in simulation process only

- - - Updated - - -




this the wave from simulation when read=1 and write =0
124 should be 124 ,112>>112 , 93>>92 and so on as shown
but when read=0 and write=1 every thing be wrong and data which copied to the file not equal to which in the memory

does my code have syntax error or just simulation process is wrong specially i use force method not test bench ?
 

The problem will be some sort of timing in your code.
If it is running, then there are no syntax errors, then the errors are yours to debug. Only you have all the code needed to run the simulation.
 

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