Measuring the leakage current of an inverter using Cadence Virtuoso

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I have an inverter at a transistor level in Cadence Virtuoso, and I want to measure its leakage current using Spectre simulator. I did a tran analysis and had a source deliver a voltage that will stabilize after some time. The problem is I don't know where to measure the leakage current. Using the to be Plotted option, I can click on the terminals of the Source, Drain and Gate of each the NMOS and PMOS transistors. Is the subthreshold leakage simply the sum of both the Drain currents?
 

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with inverter input=1, pmos drain current gives you the leakage current.
with inverter input=0, nmos drain current gives you the leakage current.

Seperate both mos inputs. Give pmos 1, nmos 0. Then measure nmos or pmos drain current. This is total leakage current.
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with inverter input=1, pmos drain current gives you the leakage current.
with inverter input=0, nmos drain current gives you the leakage current.

Seperate both mos inputs. Give pmos 1, nmos 0. Then measure nmos or pmos drain current. This is total leakage current.
 

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Solution
If I want to extend leakage measurement to 2 input gates like "AND" gates for example:
For the input 00, do I measure both nmos drain current and then sum them? But wouldn't that be weird because they are in series?
Or For the input 10, do I also sum the leakage of the drain of one pmos and one nmos that are supposed to be blocked?
 

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You have to consider drain to bulk leakage also. So, both nmos will have different IDB leakage. Measure bulk leakage by connecting dummy voltage source from bulk to gnd.
Drain to source leakage will be same for both nmos since they are in series. For this, connect dummy Vsource at 2nd nmos source to gnd. Hope this helps.
 

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I might add that the leakage current needs to be correctly modeled in your PDK models...
Some older models (i.e. BSIM3 and older) might not even contain leakage behavior.
In my experience, the threshold voltage (key parameter here) is not modeled very precisely with minimal channel length as analog designs use much longer channels than Lmin.

Leakage of digital gates should be present in PDK documentation, though...

And as people mentioned above, the total leakage is consist of several components such as drain-source tuneling leakage, gate-substrate leakage, drain-substrate, source-substrate, etc. Plus you should also consider leakage of nwell - substrate diode.
 
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So if I understood correctly, I take each transistor when it is in its off state (0 for Nmos and 1 for Pmos) and add a dummy voltage source from its bulk to gnd (or vdd), and another one from the source to the ground (or source to vdd) and add the drain current and then sum them up (and if they are in series the latter two are the same?).
Also, this may be a dumb question, but I really want to understand this: When a transistor is in its on state, but it finished transitioning can I measure also some leakage (drain-bulk and source-drain) or is it not leakage by definition?
Thank you very much for answering me.
 

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In reality, leakage current is present both in on-state and off-state, as well. Just Its value changes...
You can use "dummy voltage source" with Vdc = 0 V to measure current flow through ANY circuit branch. So yes, this way you can measure current into the gate terminal (if it is modeled) and also into/from the bulk terminal...
Just remember, current flowing into a node has positive sign, current flowing out of a node has negative sign...
 

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just keep the input(s) fixed and measure the current at VDD source. use only one source for the entire circuit, obviously. and you are done.

for multi-input gates, you have multiple input scenarios. typically we measure each separately and take the average.
 

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I might add that the leakage current needs to be correctly modeled in your PDK models...
 

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Yeah, that's correct.
Leakage will be in ON state also. To find it, you have to seperate ON current first. I don't know how to you do that.
Yes, when output is settled 100%, then you can capture leakage. But, 5tau is at infinite, right? So, still there will be a very low ON current.
 

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Hello, I want to measure the conductive current on the X3 in a device like a 4 - fan inverter. Should its value exist?
 
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Here is my code and simulation, I simulated a 4 fan inverter chain, I don't know if the measured current values are real current values, why are they all so small? Is the code I'm testing wrong?

 
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Schematic picture & plots would be good (not a fan of text method ). Just to check, is your pmos & nmos model definitions are correct? I don't see any difference except Vfbn.
 

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In fact, if I use this PMOS and NMOS model to simulate a 4-fan inverter chain, the voltage output is correct. But I don't understand why the current looks wrong.This is a transient simulation output graph.But I used dc analysis to measure the current.
 

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Isn't it DC SWEEP? I want to measure the current on the MOS tube? When I looked at the reference, I found that if I-V curves of transistors were to be obtained, VDS and VGS would need DC SWEEP.Like this.
 

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the recommendations I have seen to measure static current in std. cell libraries are usually like this: make a short transient simulation, skip the initial part of the simulation since there is a lot of noise and settling, then average the current value over time for a small time period.
 
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    shiqi

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I understand you a bit, but I'm a novice, how do you write this part of the code in HSPICE? Can you give a demonstration? 'std. cell library' What is it? Where can I find this file? Thank you for your answer, the question of current measurement has been bothering me for a long time.
But if I put a resistance R behind the X4 so that the X4 can measure the current, I don't understand why.
The value on the current of other phase inverters remains unchanged.


 

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For single mos IV curves, dc measure is fine. But in your inverter case, check transient currents.
 
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