Measuring open loop gain of LDO in LTspice

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DjAci

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I am using LTspice to model an LDO with error amplifier and an NMOS pass device and my goal is to model the open loop gain.

However i have trouble cutting the loop for AC and leaving the DC bias intact. I am using a 2 resistor voltage divider as part of the feedback loop. I can increase the value of one resistor in AC simulation to effectively cut the loop, but then i also created a massive load impedance for my AC simulation that makes problems with the output capacitor.

Does anyone know how to elegantly separate AC & DC feedback without using high value inductors and capacitors?

Edo
 

you need to design an appropriate filter in order to cut off the ac and dc signal. at the first, select the suitable cut-off frequency and design on the filter afterward.
 

did you try loopgain element as shown in loopgain2 example in LTspice examples...

I think thats the best possible way...
 

This problem - simulation of loop gain without destroying the dc operating point - has been discussed very often in detail - in this as well as in other forums. Spend some minutes and search around.

For example:
 

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