[SOLVED] Measuring Node Capacitance

I've built a ripple-carry adder in Cadence and I need to measure the capacitance at various nodes internal to my design (load capacitance at gate outputs). I realize the design is digital, but this seems to be a more appropriate forum for capacitance questions.

I need to include parasitics in my capacitance measurements, which is why I need to measure internal to my completed layout. Based on another post, it appears I should measure capacitance in Spice as follows.


First, is this an appropriate method to determine node capacitance given I need to measure internal nodes?

Second, if this is correct, is there an easy way to label/locate internal nodes based on my extracted spice model? This is a sample of what I get from Cadence.


I realize in the M378 2 3 1 0 TSMC20N that 2, 3, 1, 0 correspond to nets, but I have no idea how to discern which net is which short of drawing the entire circuit and labeling the nets. Given I have a few hundred transistors, I'd rather go a different direction.

After doing more digging I was able to label the nets within my extracted hspice model by adding pins to the layout then extracting.

Then I extracted the node capacitances by changing
to

This appears to be giving me what I want. Any obvious issues with acquiring the capacitances this way?

jasonmgeorge said:

Any obvious issues with acquiring the capacitances this way?

Click to expand...

Not at all. Within SPECTRE you may add even more detailed options to the info command: View attachment Spectre_Circ_Sim_Ref_p723.pdf

i think you can get the summary of parasitic capacitance at each node after doing layout parasitic extraction