guow06
Junior Member level 3
- Joined
- Mar 31, 2010
- Messages
- 31
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,286
- Activity points
- 1,487
I used a high voltage technology for my chip and violated some latch-up design rules. The measured power consumption is around 50 mA which is twice the simulation result.
What could be the potential reasons for that? ( my chip is pretty big and complex, so if latch-up happens, it should burn the chip instead of causing extra power. Is that correct? what else can I blame?)
What could be the potential reasons for that? ( my chip is pretty big and complex, so if latch-up happens, it should burn the chip instead of causing extra power. Is that correct? what else can I blame?)