skyjam
Newbie level 5
I'm designing a simple first-order sigma-delta modulator with RC
integrator.
Now I want to define the minimume and maximum sampling frequency of
this modulator. Of course, minimume fs can be found by investigating
the integrator output voltage --- if the fs is too low, the output
voltage will be too high to implement.
However, the maximum fs is hard to achieve. Will the system be
unstable when fs is too high? Is the maximum sampling frequency
related to the bandwidth or gain of the integrator? And How to predict
the frequency?
I'm a rookie in this field and maybe it's a silly question
But still hope to see your opinions. Thanks.
integrator.
Now I want to define the minimume and maximum sampling frequency of
this modulator. Of course, minimume fs can be found by investigating
the integrator output voltage --- if the fs is too low, the output
voltage will be too high to implement.
However, the maximum fs is hard to achieve. Will the system be
unstable when fs is too high? Is the maximum sampling frequency
related to the bandwidth or gain of the integrator? And How to predict
the frequency?
I'm a rookie in this field and maybe it's a silly question
But still hope to see your opinions. Thanks.