jkatic
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Hi,
I am designing a low power boost converter in 180nm CMOS. I am a beginner in the field, so any advice is welcome. I would like to drive my switches with maximum possible gate voltages in order to minimize their Ron (maximize efficiency) and to be safe at the same time. So, I am wondering how to determine this value? Which one of these should I follow:
1. Voltage should not exceed Vdd which is 1.8V.
2. In the PDK documentation, the BVN (for nmos) is 4.0V, but I am not sure what is this value.
3. Electrical field across gate oxide Eox=Vox/tox should be <1V/nm.
4. Vbox<12.6V warning from the tool when I sweep the gate voltage.
Thank you in advance.
I am designing a low power boost converter in 180nm CMOS. I am a beginner in the field, so any advice is welcome. I would like to drive my switches with maximum possible gate voltages in order to minimize their Ron (maximize efficiency) and to be safe at the same time. So, I am wondering how to determine this value? Which one of these should I follow:
1. Voltage should not exceed Vdd which is 1.8V.
2. In the PDK documentation, the BVN (for nmos) is 4.0V, but I am not sure what is this value.
3. Electrical field across gate oxide Eox=Vox/tox should be <1V/nm.
4. Vbox<12.6V warning from the tool when I sweep the gate voltage.
Thank you in advance.