Maximum frequency Calculation

What will be the Maximum clock frequency of the circuit?



I'm confused on which edge we will calculate the setup & hold for the latch. I guess it should be the trailing one. Any suggestions?

Assuming clk duty cycle is D. So t_cq + t_comb + t_latchsetup < t_clkperiod * D + t_Delay. From this, you can get the max allowed freqency.

Hi Kumar,


T1 T2 T3 T4
------------- -------------
| | | |
| | | |
---- ------------- -------

T1 is the launching edge of data
T1+thold --> T2-tsetup is the period available for data to be stable...as latch is transparent from T1-T2.

So setup check will be done at T2 and hold will be done at as usual T1

Min time period is

t(cell delay of flop) + t(combi delay)< T(clk period)*(1/2) - t(setup of latch) + t(skew)

so as ebuddy pointed out we can replace 1/2 in the above equation with duty cycle for generalized equation as in the above calculation I have assumed 50% duty cycle...

The fig is not so clear so uploading the attachment

Cheers,