Long term, your limit may be current density in the 1st level
interconnect, which tends to be thin and minimum-width as
well as being compromised by contact step coverage. Less
than 1mA/um of width is almost certain. If you come out the
sides, like between gate stripes, that's a problem.
Behind that you have thermal concerns, how far can you
raise the intra-device temperature before you cause some
enhanced dielectric wearout, dopant migration, etc.? The
rated operating temp will be well below this, limited by
the practicalities of qualification at extreme temps and
the limited interest of markets, in it.
Then you have the simple MOSFET channel "strength",
which imposes a minimum on-resistance which, with
your rated or actual gate oxide breakdown, sets a
current (Vgs=Vds=max)/Rds(Vds=max). Though at
an even higher voltage you could punch through and
pull plenty more current, we'll assume that you have
an interest in the second attempt looking kind of like
the first and are looking to stay out of destructive
and reliability-compromising regions of operation.
Of course if that were not true, there is plenty of
opportunity to get large currents by applying large
voltages.