subhash_chevella
Member level 3
hello all,
After synthesis, my desing has no violations in Timing. But I am getting max_transition violation? Can any one help how to fix this violation?
Required Actual Slack
oTmrTopWdRst 0.24 0.36 -0.12 (VIOLATED)
PORT : oTmrTopWdRst 0.24 0.36 -0.12 (VIOLATED)
PIN : U17/ZN 0.24 0.36 -0.12 (VIOLATED)
I tried with compile -inc -only_desgin_rule also. No improvement.
thanks & regards,
Subhash
After synthesis, my desing has no violations in Timing. But I am getting max_transition violation? Can any one help how to fix this violation?
Required Actual Slack
oTmrTopWdRst 0.24 0.36 -0.12 (VIOLATED)
PORT : oTmrTopWdRst 0.24 0.36 -0.12 (VIOLATED)
PIN : U17/ZN 0.24 0.36 -0.12 (VIOLATED)
I tried with compile -inc -only_desgin_rule also. No improvement.
thanks & regards,
Subhash