Hi,
both circuits (post#1, post#8) suffer from the same problem:
There is not true "DRIVE HIGH" according RS485.
As FvM already mentioned there should be at least
* drive high for a minimum time (driver should be active for more than 1 bit time) In best case the DRIVER_ENA is driven by the UART hardware. It should be driven HIGH (that´s what the STOP bit is for) long enough for the voltage on the cable on every point is stable with respect of signal run time and echoing.
The shown circuits are not according RS485 specification..
The given circuits may work ... or not. It depends on cabling, cable lengths, termination, pull_up ...
Just the statement "it worked in my circuit" does not mean it complies with the specification regarding voltage levels and timing. And it does not mean it is safe.
It´s like passing a crossroad without caring about traffic. It may work for days, weeks, months, maybe even years. Still it is not safe and an accident may happen at any time.
If you do a test with an eye diagram than you see that some bits are shorter and dont have equal voltage levels.
****
My personal opinion:
I say this careless designs are a reason for "sporadic fails". Some people/companies accept this sporadic fails. Some blame it on the noisy environment, some blame it on the transmitting circuit, some on the receiving circuit. Always blaming the other.
.. no one takes the responsibility for the fails of his cheap design..
"Cheap"...
A simple solution to improve performance could be to just add a capacitor for delayed DISABLE of the driver. (post#4)
Klaus