Hi,everyone
I want to write a ddr2 controller in VHDL.
Now, there is a problem in front of me.It is burst length.
In JEDEC standard its value is 4 or 8. when it's 4, it means if you write a data in location0 the location 1,2,3 in the same columne will be assert one by one.The data keep in the location 1,2,3 would be overwrite. How can i keep data safe? The length of data i will write is not fixed, but in byte.
Hi.I am writing a SDRAM's controller.
Maybe you can make some special area to store your data respectively,set some counters to store the data's address in turn.
If it is a component, DM is a good choice.But as i know, in DIMM package, DM is usually connected to VSS by mannufacture. Such as HTJ36C512x72G from micron.
Added after 11 minutes:
chrometta said:
Hi.I am writing a SDRAM's controller.
Maybe you can make some special area to store your data respectively,set some counters to store the data's address in turn.
You mean i can store a 4/8xbus_width data first, and then wirte them in one write command.That is a good idea.
But, when the address is not sequential, i think, it maybe can't work well.
DM inputs doesn't connected to the ground (Vss) in DIMM. I suppose you made such a decision based on the Functional Block Diagram (from HTJ36C512x72G specification)...
Thanks maksya!
You are right.
"If RDQS is disabled, DQS0-DQS17 bacome DM0-DM8 and DQS9#-DQS17# are not used." This description is found in HTF9C32_64_128x72 datasheet. And in the functional blcok diagram the DM is not connected to Vss also.
But, i am not sure if HTJ36C512x72G is the same. Why its datasheet don't mention it? Is it different?