[SOLVED] Max. Frequency in Cadence 130nm

Hello,

I needed to find the max. frequency that Cadence 130nm kit can support, so I designed a simple VCO using three minimum-sized CMOS inverters and I calculated the frequency of its output. Is this method correct?

Thanks,

I think it is not. It is far from the definition of transition frequency. https://analog.intgckts.com/mos-transistor/ft-of-a-mosfet/
Inverter's bias point always change under oscillation, much higher frequencies are reachable as a ring oscillator can produce.
And it doesn't represent parasitic's effect, temperature, process corners, physical implementation (layout).

frankrose said:

I think it is not. It is far from the definition of transition frequency. https://analog.intgckts.com/mos-transistor/ft-of-a-mosfet/
Inverter's bias point always change under oscillation, much higher frequencies are reachable as a ring oscillator can produce.
And it doesn't represent parasitic's effect, temperature, process corners, physical implementation (layout).

Click to expand...

I am designing a ring VCO and I needed to calculate the max. oscillation frequency on the kit, that's why I used a simple VCO design to calculate its oscillation frequency and check whether the output of my actual VCO is within the kit's limit. In this case, DO I still need to calculate the transistor's Ft?

Engineer4ever said:

DO I still need to calculate the transistor's Ft?

Click to expand...

No.
You should evaluate fmax or maximum toggle frequency.

Ring oscilator gives none of them.
https://www.edaboard.com/showthread.php?t=354854#10

1) This is not specific to Cadence but rather the foundry.
You could see a gross difference between RF-SOI 130nm
and bulk digital 130nm (which is the whole point of a RF
flow).

2) small signal fmax/fT and large signal ring oscillator
performance don't relate to each other except loosely
- Rgg and Cds for RF, IDsat and Cgg for digital

Ring oscillator frequency will change a lot depending on
whether it is held large- or small-signal. Long chains that
allow full gate logic swing are (duh) large signal and the
stage delay includes half-risetime and internal in-out
delay. Short chains or ones that are operated so current-
starved that they cannot swing far from center, will be
"small signal" (if swing is limited enough by starvation).
But now your operation is nothing like what you would
normally measure for trying to get transistor fT/fmax
(almost always set up for "bragging rights", not punked
by less-than-best biasing).

Ring oscillators of high stage count are still one of the
best ways to get at core gate performance. No, they
don't predict by themselves how fast you can self-toggle
a flip-flop (itself, only occasionally interesting) but the
observed vs modeled performance is a good feedback
presuming you account for all of the parasitics and so on.
Use the ROs for that, get the SPICE models right, and
then trust the SPICE models for the flip flops because
you just have to.