Max Frequency acheivable using 0.18u technology

• Dec 13, 2004

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mvvijay78

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Hi,
Is there any maximum frequency limit on designs that can be implemented using 0.18u technology.
Regards
Vicky

 

• Dec 13, 2004

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Puppet1

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i just saw a distributed amplifier at 35 GHz bandwidth.

 

• Dec 14, 2004

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Colbhaidh

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Typical 0.18um processes have an invertor delay of about 20-25pSecs.

 

• Dec 14, 2004

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Aormon

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We have implemented a cpu in .18 process,its clock
rate is 400Mhz.
regards!

 

• Dec 14, 2004

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qslazio

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i've design a 10GHz Balun RF circuit
the ft of mosfet in 0.18u mixed signal is about 25~35GHz

 

• Dec 14, 2004

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nitu

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Colbhaidh said:

Typical 0.18um processes have an invertor delay of about 20-25pSecs.

Click to expand...

Can you elaborate the term invertor delay (what is stage ratio) and typical....

 

• Dec 15, 2004

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niuniu

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usually a complex pure digital system using synthesis method can reach 200MHz.

 

• Dec 15, 2004

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diablo1222

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If use standard cell, it can work at 600 Mhz for simply design (tsmc 0.18).

 

• Dec 15, 2004

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icsrc

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as for dsp core ,100~200MHz for general design

 

• Dec 16, 2004

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luxboy

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It's design and process depended.
If CMOS process used, cannot reach Giga level.
Good library and layout design could achieve good result

 

• Dec 17, 2004

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kelvin_sg

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When I was coding an F/N PLL, 250MHz was no big deal if I tweak the code a bit.

 

• Dec 18, 2004

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liaotao

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i have a mips cpu design at 400Mhz

 

• Dec 18, 2004

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Each CMOS process has its limit.

In digital design at least you have delay of one inverter that impose a maximum theoretical limit on switching frequency and speed.

In analog, you have the same limit but you can determine it with the fastest possible amplifier. Our master says that a folded cascode amplifier with good layout is the fastest amplifier that can be implemented.

 

• Dec 28, 2004

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xworld2008

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At .18 a invertor cell which have one input and four output which dely is 20~50 psec, so if the freq is 1G
then from DFF to the next Dff is 1ns, so at the DFF to the next DFF it just can have 20~50 cell. If you can write rtl good , it will work good. But i feel the freq 300~600M is the freq of limit .18.

 

• Dec 29, 2004

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Max Frequency that can be acheived is a function of the way you implement your hardware.

So you should look into the longest combinational path that you have in your design. This will control the max frequency as compared to the process(0.18u)

 

• Dec 29, 2004

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was this question for digital logic or analog circuits ?

razavi did 40GHz in 0.18umCMOS while heydari did 35GHz distributed amp as i mentioned

 

• Jan 8, 2005

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mvvijay78

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Hi,
Can anyone comment if it is a standard that we have to choose from some standard die sizes acvailable from any foundry.
Vicky