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[SOLVED] Matching 50 Ohm to LNA - Cadence simulatuon

Minh_Hoang_Le

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Hello, I am a student and I have a question when doing my project that cannot answer. I am designing an impedance matching network to match a 50 Ohm source to the LNA (modelled with L-bonding and C-pad). The input impedance of the LNA with L-bonding and C-pad is Zin=8.815-54.2j. I designed a LC-network in figure 1 to make a narrowband matching based on this Zin. The S11 at 1 GHz is very good, however, the S21 is negative (attenuation). I played with the LC network and see that when I made a LC series network (figure 2), the S11 degraded into such a wideband matching, but the S21 improves significantly. The S-parameter responses of these 2 cases are in figure 3.

I checked the DC biases in the two cases, all are the same and work correctly. About the port instance, I setup like in figure 4, one port at the input of the impedance matching network, the other port at the output of the LNA with one DC block capacitor in the middle of the LNA and the port instance. I choose the amplitude to be -30 dBm to represent a 20 mV peak-to-peak signal fed into the LNA. My SP setup is in figure 5.

The narrowband impedance matching network seems to be good at both matching and maximum power transfer, however, I do not understand why its S21 is so bad.

Figure 1
1742569045757.png


Figure 2
1742569243600.png


Figure 3 - the yellow curves match to the network in figure 1, and the red curves match to the network in figure 2
1742569375124.png


Figure 4
1742569703753.png


Figure 5
1742569894463.png
 
Last edited:
Solution
I realize that just by changing the LC network from figure 1 to figure 2, the DC biasing at the input change from 100 mV to 350 mV.... but I do not understand this.
The circuit in fig1 has no DC block, so the 50 Ohm port impedance will load any DC voltage on that net. DC current will flow into the port.

The circuit in fig2 has the series capacitor that blocks DC from flowing into the 50 Ohm port impedance.
I realize that just by changing the LC network from figure 1 to figure 2, the DC biasing at the input change from 100 mV to 350 mV.... but I do not understand this. The L and C components I use are ideal components from analoglib. I choose the resistance of the L component to be 1 Ohm for estimation.
 
I realize that just by changing the LC network from figure 1 to figure 2, the DC biasing at the input change from 100 mV to 350 mV.... but I do not understand this.
The circuit in fig1 has no DC block, so the 50 Ohm port impedance will load any DC voltage on that net. DC current will flow into the port.

The circuit in fig2 has the series capacitor that blocks DC from flowing into the 50 Ohm port impedance.
 
Solution


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