[SOLVED] Mask Fabrication Workflow

[melkord]

Hi,

I have these questions about the mask fabrication or mask design.

Let's say we have already a layout of an OpAmp or a (simple) processor we want to fabricate complete with the pads.

my questions:

1. is the pattern in the layout the same with the pattern in the mask?

2. There is this term in Lithography called Resolution Enhancement Techniques (RET).
The pattern in the mask are different with the pattern we are expecting to be there on the wafer.
For example, the mask have this sherrif pattern in the corner, etc.
Who takes care about this pattern? Is it the layout engineer?

3. Should the layout engineers keep this RET in mind while they are making the layout?


Reference:
https://en.wikipedia.org/wiki/Computational_lithography

 

[erikl]

1. No. At least in deep submicron processes, for each layer or fabrication step exposure several masks are used to allow for wafer structures (well) below the light wavelength used.

2. No, it's done automatically by fab/foundry engineers, using elaborate computer programs.

3. Again NO. It's totally sufficient if you don't violate the many many design rules!