[SOLVED] Mapping unknown (X) to 0/1 in VCS

[kyonglee]

Hi,

I am using VCS for a gate level netlist simulation of my design.
When my design doesn't meet timing constraints, i.e., setup time and hold time, VCS spits out X's. For my own purpose, I want to map these X's to 0/1's with equal probability and continue to simulate. Can I even do this in VCS? If so, how can I do that?

Many thanks!

 

[kornukhin]

"The VCS command line plusarg option +notimingchecks disables all Setup and Hold checkings of all the design. "

 

[phixcoco]

I am using VCS for a gate level netlist simulation of my design.
When my design doesn't meet timing constraints, i.e., setup time and hold time, VCS spits out X's. For my own purpose, I want to map these X's to 0/1's with equal probability and continue to simulate. Can I even do this in VCS? If so, how can I do that?

kyonglee,

(1) Follow kornukhin's instruction by turning off time violation check first, X from timing violate cells will disappear. But in 4-state simulation, it's a large chance, you'll still meet X during gate-level simulation. They are rooted in uninitialized registers or mems, some may merely x-propagation issues, some may real bugs, so don't get annoyed by Xs in waveform

(2) You can try 2-state simulation in vcs by applying +2state flag to your command. Pls do read vcs's manual and searching the internet for prons and cons of 2-state simulation.