Mapper block for TX(512)

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Kosyas41

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Hello,
Im faced with problem how to write mapper.The main purpose of this mapper is produce packages which looks like [000001data1data1data1data1 ....00000].Data I can get from PRBS with the next code
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity random is
    generic ( width : integer :=  32 ); 
port (
      clk : in std_logic;
      random_num : out std_logic_vector (width-1 downto 0)   --output vector            
    );
end random;

architecture Behavioral of random is
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;
end;
the total length of one package from mapper is 512.Could you pls give me some help with this task
 

i have this code but its still not working
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;


entity mapper_1 is 
port (	
			clk: in std_logic;
			data_in : in std_logic_vector (9 downto 0);
			data_out : out std_logic_vector(10 downto 0)
);
end mapper_1;
architecture mapper_arch_1 of mapper_1 is 
--default state
constant min_count : integer :=0;
--signal one : std_logic_vector(0 downto 0) :="1";
----
constant max_count : integer :=511;
begin
process(clk)
	variable cnt : integer range min_count to max_count;
	variable n : integer :=0;
begin
cnt:=0;
cnt :=cnt +1;
if cnt < 8 then
--if data_in < 8  then
	data_out <="00000000000";
	end if;
if cnt = 9 + 10*cnt then
	data_out <="11111111111" ;
	end if;
if cnt = 14 + 10*(cnt+1) then 
data_out <="01010101010";
end if;
--cnt := cnt +1 ;
--n := n + 1;

end process;
end mapper_arch_1;
 

VHDL is not a software programming language don't use it as a programming language. Stop using variables, if you don't know how to code it using SIGNALs then you shouldn't be using variables.

Things such as:
Code: 
cnt:=0;
cnt :=cnt +1;

doesn't result in cnt being set to 0 only the increment cnt is implemented as this is VHDL and not a programming language. You also are using integer types (integer type is a 32-bit value) which are a fixed bit width and may therefore result in unexpected results.

Get a VHDL book and if you are weak in digital design get a good digital design book learn the digital design and apply that knowledge to writing VHDL that describes a digital circuit.

Given you are writing a program your program will likely only count to 1 as every time the process is entered on clk edges (both edges) it will set the variable cnt to 0 then increment it immediately (you won't even see the 0).

Code VHDL - [expand]
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signal clk, rst : std_logic;
signal cnt : unsigned(7 downto 0);
 
-- counter code
process (clk, rst)
begin
  if (rst = '1') then
    cnt <= (others => '0');
  elsif rising_edge(clk) then
    cnt <= cnt + 1; -- or it might require cnt + to_unsigned(1) (I'm not a big VHDL user)
  end if;
end process

The above code will implement a resetable rollover counter i.e. counts from 0-255-0-255-...
 

thanks for reply,based on your comments I write my code like this,but I have small question,about if loop,usually the number which mentioned before if (like 8,13,17,21...)they are incremented by 5 every loop until they will reach 512.Could you pls give me some hint or example how can I create loop for this increment ?
Code: 
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity mapper_1 is 
port (	
			clk, rst: in std_logic;
			data_in : in std_logic_vector (3 downto 0);
			data_out : out std_logic_vector(27 downto 0)
			--data :out std_logic_vector(30 downto 0)
);
end mapper_1;
architecture mapper_arch_1 of mapper_1 is 
constant begining : integer :=000000001;
constant ones : integer := 1;
signal cnt : unsigned (9 downto 0);
signal data_out1 : std_logic_vector (12 downto 0);
signal data_out_2 : std_logic_vector (17 downto 0);
signal data_out_3 : std_logic_vector (22 downto 0);
begin

process(clk,rst)
begin
	if (rst ='1') then
		cnt <= (others =>'0');
	elsif rising_edge(clk) then
		cnt <= cnt + 1;
	if cnt =8 then
		data_out1 <=  conv_std_logic_vector(begining,9) & data_in;
	elsif cnt = 13  then
		data_out_2 <= data_out1 & conv_std_logic_vector (ones,1) & data_in;
	elsif cnt = 17 then
		data_out_3 <= data_out_2 & conv_std_logic_vector (ones,1) & data_in;
	elsif cnt = 21 then
		data_out <= data_out_3 & conv_std_logic_vector (ones,1) & data_in;
end if;
end if;
end process;
end mapper_arch_1;

because if I write like this
Code: 
elsif cnt = 21 + cnt *3 then
I got the error "Cant determine definition of operator"
 
Last edited:

try using ieee.numeric_std rather than std_logic_arith, because std_logic_arith is not a standard VHDL library.

Please post the whole code with the problem, rather than an out of context snippet.
 

the whole code looks like
Code: 
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity mapper_1 is 
port (	
			clk, rst: in std_logic;
			data_in : in std_logic_vector (3 downto 0);
			data_out : out std_logic_vector(27 downto 0)
			data_out_1 :out std_logic_vector(2 downto 0)
);
end mapper_1;
architecture mapper_arch_1 of mapper_1 is 
constant begining : integer :=000000001;
constant ones : integer := 1;
signal cnt : unsigned (9 downto 0);
signal data_out1 : std_logic_vector (12 downto 0);
signal data_out_2 : std_logic_vector (17 downto 0);
signal data_out_3 : std_logic_vector (22 downto 0);
begin

process(clk,rst)
begin
	if (rst ='1') then
		cnt <= (others =>'0');
	elsif rising_edge(clk) then
		cnt <= cnt + 1;
	if cnt =8 then
		data_out1 <=  conv_std_logic_vector(begining,9) & data_in;
	elsif cnt = 13  then
		data_out_2 <= data_out1 & conv_std_logic_vector (ones,1) & data_in;
	elsif cnt = 17 then
		data_out_3 <= data_out_2 & conv_std_logic_vector (ones,1) & data_in;
	elsif cnt = 21 then
		data_out <= data_out_3 & conv_std_logic_vector (ones,1) & data_in;
        elsif cnt = 21 + cnt *3 then
                data_out_1 <="001"
end if;
end if;
end process;
end mapper_arch_1;
the problem is how to create a loop for cnt,because it incr by 5 until 511
 

What are begining and ones supposed to be? they are the same value. Why are you using them.
Cnt is incrementing by 1 on each clock cycle - why do you think it is incrementing by 5.
Please switch to using numeric_std, not std_logic_arith.
 

I wanted to get data_out with 512 width.so data_out should looks like somezeros1data_in1data_in1...somezeros
 

but data_out is only 28 bits wide, so it cannot hold 512 bits
 

so final code looks like this
Code: 
----mapper
--signal_out[0000001data1data1data.......100000000]
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity mapper_1 is 
port (	
			clk, rst: in std_logic;
			data_in : in std_logic_vector (31 downto 0);
			data_out : out std_logic_vector(511 downto 0)
			--data_out_n : out std_logic_vector (1 downto 0)
);
end mapper_1;
architecture mapper_arch_1 of mapper_1 is 

--constant min_count : integer :=0;
constant begining : std_logic_vector :="000000001";
constant ending : std_logic_vector := "00000000";
constant ones : std_logic_vector := "1";
--constant max_count : integer :=511;
signal cnt : integer range 0 to 511;
signal data_out_1 : std_logic_vector (8 downto 0);
signal data_out_2 : std_logic_vector (41 downto 0);
signal data_out_3 : std_logic_vector (74 downto 0);
signal data_out_4 : std_logic_vector (107 downto 0);
signal data_out_5 : std_logic_vector (140 downto 0);
signal data_out_6 : std_logic_vector (173 downto 0);
signal data_out_7 : std_logic_vector (206 downto 0);
signal data_out_8 : std_logic_vector (239 downto 0);
signal data_out_9 : std_logic_vector (272 downto 0);
signal data_out_10 : std_logic_vector (305 downto 0);
signal data_out_11 : std_logic_vector (338 downto 0);
signal data_out_12 : std_logic_vector (371 downto 0);
signal data_out_13 : std_logic_vector (404 downto 0);
signal data_out_14 : std_logic_vector (437 downto 0);
signal data_out_15 : std_logic_vector (470 downto 0);
signal data_out_16 : std_logic_vector (503 downto 0);
signal data_out_17 : std_logic_vector (511 downto 0);
begin

process(clk,rst)
	--variable temp_out : std_logic_vector(511 downto 0);
	--variable temp_out_1 : std_logic_vector(12 downto 0);
begin
	if (rst ='1') then
		cnt <=0;
	elsif rising_edge(clk) then
		cnt <= cnt + 1;
--for i in 0 to 511 loop
--if cnt = 0 then
--temp_out_1 := conv_std_logic_vector(borders,8) & conv_std_logic_vector(ones,1) & data_in;
--data_out_1 <= temp_out_1;
--elsif cnt = 502 then
--temp_out := data_out_1 & conv_std_logic_vector(borders,8);
--data_out <= temp_out;
--elsif cnt =9 then
--temp_out := conv_std_logic_vector(ones,1) & data_in & conv_std_logic_vector(ones,1);
--data_out <= temp_out;
	if cnt =9 then
		data_out_1 <=  begining;
	elsif cnt = 42  then
		data_out_2 <= data_out_1 & data_in & ones;
	elsif cnt = 74 then
		data_out_3 <= data_out_2 & ones & data_in;
	elsif cnt = 107 then
		data_out_4 <= data_out_3 & ones & data_in;
			elsif cnt = 140 then
		data_out_5 <= data_out_4 & ones & data_in;
			elsif cnt = 173 then
		data_out_6 <= data_out_5 & ones & data_in;
			elsif cnt = 206 then
		data_out_7 <= data_out_6 & ones & data_in;
			elsif cnt = 239 then
		data_out_8 <= data_out_7 & ones & data_in;
			elsif cnt = 272 then
		data_out_9 <= data_out_8 & ones & data_in;
			elsif cnt = 305 then
		data_out_10 <= data_out_9 & ones & data_in;
			elsif cnt = 338 then
		data_out_11 <= data_out_10 & ones & data_in;
			elsif cnt = 371 then
		data_out_12 <= data_out_11 & ones & data_in;
			elsif cnt = 404 then
		data_out_13 <= data_out_12 & ones & data_in;
			elsif cnt = 437 then
		data_out_14 <= data_out_13 & ones & data_in;
		elsif cnt = 470 then
		data_out_15 <= data_out_14 & ones & data_in;
				elsif cnt = 503 then
		data_out_16 <= data_out_15 & ones & data_in;
				elsif cnt = 511 then
		data_out <= data_out_16 & ending;


		
--data_out <= conv_std_logic_vector(begining,9) & data_in& '1'&data_in; 
--if cnt < 8 then
--	data_out <="00000000000";
--	end if;
--if cnt = 9 then
--	data_out <="11111111111" ;
--	end if;
--if cnt = 10 then 
--data_out <="01010101010";
--end if;
--cnt := cnt +1;
--data <= data_out+data_out;

--end if;
end if;
--end loop;
end if;
end process;
end mapper_arch_1;

- - - Updated - - -

but now I have a problem Quartus cant fit your design(
 

I assume the problem is not enough pins on the device. WHat are you expecting to connect all 512 data bits to?
 

I want to do mapper for FFT engine (512) so,I have PRSG which generate random data,after this mapper makes mapping of those data which come from PRSG.Data after mapping should looks like (some zeros 1 data 1 data ...1 some zeros)
My device is Cyclone IV E
or mb I dont understand what does it mean std_logic_vector (511 downto 0)
 
Last edited:

You havent posted the quartus error.
Also - have you simualted your design? does it work as expected?
 

i cant simulate it with my device because I have an error like "
Code: 
Error (119027): Design requires 546 I/O pad resources -- too many to fit in 544 available in the selected device or any device in the device family
Error (119003): Cannot find device that meets Compiler settings specifications
Error: Quartus II 64-Bit Fitter was unsuccessful. 2 errors, 0 warnings
	Error: Peak virtual memory: 953 megabytes
	Error: Processing ended: Wed Aug 10 09:59:51 2016
	Error: Elapsed time: 00:00:02
	Error: Total CPU time (on all processors): 00:00:03
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 33 warnings

- - - Updated - - -

my FTT length is 512
when I choose different device and its works as I want

- - - Updated - - -

mb I should do std_logic_vector (8 downto 0)
 

Your error implies that you are trying to compile your design in Quartus - this is a compillation tool, not a simulation tool. You need to use something like modelsim
It is trying to map all of your ports to output pins, and there simply are not enough on your device. But you wouldnt want to do this anyway as connecting a 512 bit bus to anything in the outside world is just going to be impossible.
 

thanks for reply,I chanched my code/now it works as I want
Code: 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity mapper_2 is 
port (	
			clk,rst : in std_logic;
			data_in : in std_logic_vector (2 downto 0);
			data_out : out std_logic_vector(14 downto 0)
);
end mapper_2;
architecture mapper_2_arch of mapper_2 is 
--signal  rst : std_logic;
signal cnt : unsigned(8 downto 0);
constant zeros : std_logic_vector :="000";
constant ones : std_logic_vector  := "1";
constant zero : std_logic_vector  := "0";
signal out_t : std_logic_vector(3 downto 0);

signal out_t_1 : std_logic_vector(7 downto 0);
signal out_t_2 : std_logic_vector(11 downto 0);
begin 
-- counter code
process (clk, rst)
begin
  if (rst = '1') then
    cnt <= (others => '0');
  elsif rising_edge(clk) then
    cnt <= cnt + 1; 
  if cnt = 3 then
  out_t <= zeros & ones;
  elsif cnt = 7 then 
  out_t_1 <= out_t & data_in & zero;
  
  elsif cnt = 11 then
  out_t_2 <= out_t_1 & data_in & ones;
 elsif cnt = 15 then
data_out <= out_t_2 & zeros;
--  end if;
  end if;
  end if;
end process;
end mapper_2_arch;
 

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