Map report remove most coregen blocks and designed this as Loadless

[antonkurka]

In my design in the process runangle I use a lot of coregen5.0 CORES specifically:
Floating Point: mul,div,sqrt,add,sub which were correctly declared as components and
implemented as ----.xco.
The results of individual cores are used as inputs of the next one,
there is no Core-output (result) that is not connected.
In The Map report are most of it is referred to as a loadless block and is removed.
see appendix modul RUNANGLE and the implementation at the end of the module and Map report
What is the reason for this?

My tool is ISE 14.7, Target is Kintex7_325,coregen is 5.0 version

 

[dpaul]

@antonkurka
If your logic block is not driving any outputs, then synthesis tools removes such blocks of logic. Most probably this is happening.

 

[antonkurka]

@antonkurka
If your logic block is not driving any outputs, then synthesis tools removes such blocks of logic. Most probably this is happening.

No, only one component is not connected (only for testing) otherwise all outputs (results)
from all CORES are connected either to the input of the next CORE or to the chip output (entity output).
I have checked everything again. Regards Anton

 

[dpaul]

No, only one component is not connected (only for testing) otherwise all outputs (results)
from all CORES are connected either to the input of the next CORE or to the chip output (entity output).
I have checked everything again. Regards Anton

Really? Did you carefully study the synthesis report posted here?

 

[antonkurka]

Hi dpaul
Thank You for replay.
I think several processes have a problem, so I want to test them one by one separately first
So I created the process "RunAngle" for testing as Entity RunAngle to eliminate external influences.
After compilation, all !! components that are used from IP coregen are removed from the MAP. These are the following IP cores: FloatingPoint: Mul,Div,Add,Sub.
What could be the reason that all IP cores are removed?
In the simulation (Modelsim), all cores work correctly.
Do the coregen IP floating point cores from ISE14.7 no longer work for the implementation?
"Regenerate All cores" didn't help.
Is it possible to download a working update?
The latest update (2020) is only offered for WM, ISE14.7, otherwise the old update from 2013 corresponds to my version.
How can I use the VM version with modelSim?
Greetings Anton

 

[std_match]

Where is the test bench?
Also, you are using "wait until (rising_edge(clk));" in the process.
I don't know what happens with such a construct in synthesis. I would expect an error.
Please change to
"process(clk)"
and
"if rising_edge(clk) then"

 

[dpaul]

@antonkurka

-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on

Can that be a problem for removal?
There would be no problem sin sim, but synthesis engine might have a problem.

 

[dpaul]

Where is the test bench?
Also, you are using "wait until (rising_edge(clk));" in the process.
I don't know what happens with such a construct in synthesis. I would expect an error.
Please change to
"process(clk)"
and
"if rising_edge(clk) then"

Good catch @std_match, I went through the OP's RTL yesterday in serach of what parts of logic could be removed but my eye had missed that.
Now that is really a red flag - in my opinion the OP needs to review his/her VHDL knowledge.