syedshan
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Dear all,
I am having the following error while doing Mapping phase of the design...But I can't understand why previously I did not get this error
Now I understand that I have to insert IDELAYCTRL somewhere, but previously I never added this in the reference design that I am using.
and that design worked fine since it was provided by the company who provided the board and reference designs...
Now that I change only my code for storing and retreiving data and so on without changing the parts which are responsible for communication with
ADC, i.e. I did not changed IBUFDS and IODELAYE1 etc. things since I have only bookish idea of these things...
Then why am I getting these errors...
Also how to deal with these errors now that I am having it (of course I am looking for material but any expert solution would be helpful)
By the way the code snippet is as below...
Waiting for replies.
Bests,
Shan
I am having the following error while doing Mapping phase of the design...But I can't understand why previously I did not get this error
Now I understand that I have to insert IDELAYCTRL somewhere, but previously I never added this in the reference design that I am using.
and that design worked fine since it was provided by the company who provided the board and reference designs...
Now that I change only my code for storing and retreiving data and so on without changing the parts which are responsible for communication with
ADC, i.e. I did not changed IBUFDS and IODELAYE1 etc. things since I have only bookish idea of these things...
Then why am I getting these errors...
Also how to deal with these errors now that I am having it (of course I am looking for material but any expert solution would be helpful)
By the way the code snippet is as below...
Code:
-- Use LVDS buffers in HPC and LPC mode when LVDS is selected
cha_lvds_bufs: if (CMOS_N_LVDS = '0') generate
data_a: for i in 0 to RESOLUTION/2-1 generate
-- Differantial input buffer
ibufds_inst : ibufds
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map (
i => cha_p(i),
ib => cha_n(i),
o => cha_ddr(i)
);
-- Input delay
iodelay_inst : iodelaye1
generic map (
IDELAY_TYPE => "VARIABLE",--"FIXED",
IDELAY_VALUE => CHA_IDELAY,
DELAY_SRC => "I"
)
port map (
DATAOUT => cha_ddr_dly(i),
IDATAIN => cha_ddr(i),
c => clk,
ce => ce_a,
inc => inc_a,
datain => '0',
odatain => '0',
clkin => '0',
rst => rst,
cntvaluein => conv_std_logic_vector(CHA_IDELAY, 5),
cinvctrl => '0',
t => '1'
);
-- DDR to SDR
iddr_inst : iddr
generic map (
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map (
q1 => cha_sdr(2*i),
q2 => cha_sdr(2*i+1),
c => clk_ab,
ce => '1',
d => cha_ddr_dly(i),
r => '0',
s => '0'
);
end generate;
end generate cha_lvds_bufs;Waiting for replies.
Bests,
Shan
Last edited: