manchester encoding - how does it recover the clock

[keremcant]

hi,
how does sending the data encoded with manchester scheme help us recover the clock. (except that it has more transitions in it than the not encoded data).
what kind of a circuit recovers the clock from the encoded data?
thanks

 

[FvM]

A circuit, that is sensitive to signal transitions of both polarities can recover the clock from manchester encoded data. To lock to the clock phase, a preamble or some other kind of embedded sync signal is required however.

 

[keremcant]

A circuit, that is sensitive to signal transitions of both polarities can recover the clock from manchester encoded data.

what do you mean by that? it has to be some kind of a PLL, I guess, right? but for the PLL to be able to adjust its output according to the input signal, the input signal has to be periodic, however that's not the case in manchester coding. am I wrong?

 

[bigdogguru]

Here are some links to a reasonable good tutorial and presentation on Manchester Encoding:

**broken link removed**

**broken link removed**

I also have posted over a dozen more links concerning Manchester Encoding and its implementation on various platforms in the new group:

Embedded Wireless Networks

You are more than welcome to browse them, just look for the thread entitled EWN - Manchester Encoding/Decoding RF Applications.

Hope the info helps answer some of your questions.

 

[FvM]

it has to be some kind of a PLL

Yes, but not a PLL with a standard phase comparator. You placed the question in the microcontrollers forum. IN a microcontroller, you can implement a software PLL that tracks a low low data rate manchester encoded stream, e.g. in a radio protocol.

You can also refer to costas loop PLL, that is able to lock to a phase shifted binary modulation. It's e.g. used in GPS decoding.

 

[keremcant]

hi bigdogguru,
thanks for the reply, I think I found the part realted to my question. in the first link you have recommended it says:

"Clock synchronization
Another intrinsic value to Manchester encoding is the fact that the synchronizing clock is embedded within the signal. This fact is exploited in Ethernet, which uses on-board circuitry to maintain clock synchronization. A Digital Phase Locked Loop (DPLL) circuit monitors the incoming Manchester-encoded signal and makes adjustments to its internal oscillator to keep it in constant synchronization with the transmitter's clock frequency.

The DPLL functions by sampling the incoming Manchester-encoded data with its own local clock. A simple shift register, driven by the local clock, accumulates all the shifted bits.

If the local oscillator is in synchronization with the transmitter's clock, there will be an equal number of binary 1's and 0's across the shift register. If an imbalance occurs between binary 1's and 0's, the local clock is adjusted based on the number of binary bits off center. This is why you will find a preamble at the beginning of each packet transmitted via Ethernet. "

but why do the numbers of 1's and 0's have to be equal?

 

[bigdogguru]

So, there's no DC component.

The DC component of the encoded signal is not dependent on the data and therefore carries no information, allowing the signal to be conveyed conveniently by media (e.g. Ethernet) which usually do not convey a DC component.

 

[FvM]

So, there's no DC component.

The question was about a criterion to adjust a clock phase, not about DC balance of the data stream.

I fear the quoted statement about clock synchronization doesn't describe the method exactly. The sync methods I know are for packet like manchester encoded data. Here a preamble is used to synchronize the bit and word boundary at the same time. From there on, the regenerated clock is simply tracking the edges.

 

[keremcant]

yeah, I couldn't get the "no DC" statement either?

but FvM, if it was not doing any clock generation after the preamble and simply used the with the preamble generated clock, then why would we need the manchester coding at all? so I guess there is something more?..

 

[FvM]

so I guess there is something more?..

Yes.
1. The DC balanced property of the modulated signal, which is in fact substantial for many applications
2. You have continuous edges for constant '0' or '1' data, which is the prerequisite to track the clock phase over longer data packets.

As a general comment, manchester encoding is a simple method to achieve the said objectives. It's e.g. used in 10 MBit/s ethernet. Fast protocols (as 100 and 1000 MBit/s ethernet, or SATA, PCIe...) are using more effective methods like 8b/10b encoding.

 

[bigdogguru]

but why do the numbers of 1's and 0's have to be equal?

My mistake, I thought your question above was referring to something else.

It's been a long day.

It's been my understanding that a balanced data pattern, containing equal numbers of 0's and 1's, provides for guaranteed clock transition synchronization for the receiver.

It also has the added benefit of creating an even power value.

 

[FvM]

It's been my understanding that a balanced data pattern, containing equal numbers of 0's and 1's, provides for guaranteed clock transition synchronization for the receiver.

There may be a general method to synchronize the clock phase for continuous manchester encoded data I'm not yet aware of. But I rather guess it doesn't exist.

Unlike 8b/10b, manchester encoding doesn't provide unique sync characters. So an explicite synchronization, e.g using a preamble will be necessary. If you look at the encoded stream, you won't be able to distinguish between constant '0' and constant '1', nor to identify the bit boundaries in this special case.