Making layouts with MOSIS scalable rules

Hello,

Since I dont have any pdks at my end, I wanted to use mosis scalable CMOS rules for making layouts. I found the rules for minimum distances and SPICE file at mosis site. I have two queries regarding the same:

** Where will I find the corresponding RLC and parasitics information of layers. If the answer is no, what is the way around the problem pls.

** How to input the design rule information and the RLC & parasitics information in the tools (viz tanner etc) as ready made files are not available.
Also, if the ready made files are available, where to find them pls.

Also, are there any general pdks freely available. If so, pls. let me know.

Thanks,
Hobbyiclearner

Check out LASI, there are some PDKs for it (incl some
MOSIS foundries). DRC but no LVS, other than you can
netlist the layout to SPICE and check function crudely.
I would imagine that you could inspect the DRC rules
tile for XY groundrules.

For RLC you'd have to drill into the foundry and see if they
left any layer thickness info laying around where people
can get at it. May find stray local copies of MOSIS docs
bu web searching, universities are often careless about
securing students' or teaching assistants' data. If you
have thicknesses then you can calculate "close enough"
R and C; L is just line length if aspect ratios L/W, L/t are
high.

Might also look at "gpdk" but last I did, it only focused on
some deeper submicron stuff that I had no interest in.

Thanks for the reply dickfreebird. Yes, though LASI contains the PDKs, I am comfortable with Tanner. Hence, is there any tool in your info which can convert pdks in .tdb (tanner format). Also, it may be easier to use an integrated set of tools rather than installing lasi, winspice etc.

Hobbyiclearner.