MAking a core of my VHDL project

Thread starter John_Sanders
Start date Apr 9, 2013

Status: Not open for further replies.

Apr 9, 2013

John_Sanders

Newbie level 3

Dear All

Is it possible to make a soft core for my project which i designed using VHDL. i mean that if i need to share the synthesized project, i don't need to share the code just the softcore; the output and input pins of which are only visible and not any part of coding. Please help me guys its urgent

i used Xilinx ISE design suite to make my project on spartan 3e 1200k

Thanks

Status: Not open for further replies.

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MAking a core of my VHDL project

John_Sanders

Newbie level 3

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