Major FPGA manufacturers SRAM vs FLASH

[shaiko]

Hello,

With the important advantages of FLASH technology over SRAM (mainly power savings and non volatility) it seems that the motivation to use SRAM FPGAs comes mostly from the more advanced silicon (22nm vs 90nm) process - which is 2 leaps ahead of FLASH.

But because of the boundries of Moores law - FLASH will eventually catch up...

So, do you think that Altera/Xilinx will switch to FLASH someday ?

 

[kemiyun]

I'm not sure but any non volatile memory as far as I know will not be as fast as an SRAM. They will also require an interfacing circuit between Flash and other logic. As the clocks of FPGA's are still at lower frequency relative to ASICs, I do not believe they will switch to Flash until it becomes fast enough. But why not in the future

 

[FvM]

I recently had the oppportunity to work on a design for an Actel IGLOOe FPGA. I think the devices are interesting for a number of applications, but performance-wise can't compete with latest SRAM based devices.

 

[keith1200rs]

I am looking at Actel Igloo as well for a project. They are designed for low power rather than speed anyway, so I am not sure the fact that they are flash would necessarily be the cause of the slower speed.

To come back to the original question, on reason for devices not being flash based could be that it requires different processing steps to include flash in a CMOS process?

Keith

 

[shaiko]

Not to include flash in a CMOS process (although Xilinx did it with the Spartan 3AN)
I was asking about the possibily that Altera/Xilinx will abandon SRAM technology and switch to FLASH.
When SRAM technology will have no where to shrink anymore (because of the limits of Moore's law) it may take FLASH only a few years to catch up and reach the same endpoint geometry...When this happens, do you think that Altera/Xilinx will adapt FLASH instead of SRAM ?

 

[keith1200rs]

Moores law isn't a law or a limit - it was a projection or prediction. It doesn't dictate anything.

I think that the choice of SRAM versus flash is based on cost. On that basis mainstream FPGAs will stay SRAM as Flash will always cost more. I cannot see it being a speed issue. It is a competitive business and chip cost matters.

Keith

 

[shaiko]

So...you're saying that 10 years from today when SRAM and FLASH will have the same nm geometry Altera and Xilinx will still be making SRAM ( and only SRAM) devices ?

 

[FvM]

"Include flash in CMOS" can mean quite different things. Having a standard CMOS FPGA loaded from a built-in flash, as in XILINX 3AN or Altera MAX II/V, or building flash cells inside the logic arrays. In the latter case, you partly give up the advantages of truely complementary logic cells with zero static power consumption.

I see various points against flash technology used in highest density and speed FPGAs.

 

[shaiko]

I meant the first option...
for some reason - neither Altera nor Xilinx made anymore devices with the flash inside (other then the SPARTAN 3AN and XP2 from lattice).
Do you know the reason for that ?

 

[joelby]

It could be that the market just wasn't very interested in integrated flash. Maybe everyone wanted to store configurations on SD or CF cards, or do multi-boot and partial reconfiguration and this wasn't possible with the limited amount of integrated flash available, or the cost of the integrated devices was higher (from memory, it was a two die chip, so the two silicon processes must have been different) than using separate FPGA and configuration PROM chips, and the space and BOM saving was rarely justified.

 

[RetroTechie]

Surprised no-one has mentioned this yet, but another problem with Flash is its limited number of re-writes.

For a FPGA in a relatively static application (like in most consumer electronics?) this wouldn't be an issue. But there are surely FPGA uses where the FPGA is re-configured (differently!) many times, say some high-performance computing or scientific applications. Integrated Flash might wear out in such uses, and then the FPGA becomes defect / useless.

Probably not the reason for Flash based vs. SRAM-based market %, but possibly a reason contributing to what others already said.

 

[FvM]

I agree, that limited programming cycles of flash storage are a point, also possibly limited guaranteed lifetime of stored information.
The problem however won't count in most applications. I have a measurement module design based on Altera MAX II (a so-called CPLD, actually small SRAM based FPGA with built-in configuration and user flash) with nominal 100 programming cycles minimum, it's also storing calibration information in the flash. But it's very unlikely to reach the cycle limit in a product lifetime of e.g. 30 years.

An Altera FAE told me some time ago, that they have been considering larger FPGA with built-in configuration flash, not flash logic cells. In other words something similar to Spartan 3AN or respective Lattice devices, but it would end up in a multi chip package and thus not fit small form factors. Apparently the market demand hasn't be strong enough to bring on this idea.

 

[j.perkins]

Surprised no-one has mentioned this yet, but another problem with Flash is its limited number of re-writes.

For a FPGA in a relatively static application (like in most consumer electronics?) this wouldn't be an issue. But there are surely FPGA uses where the FPGA is re-configured (differently!) many times, say some high-performance computing or scientific applications. Integrated Flash might wear out in such uses, and then the FPGA becomes defect / useless.

Probably not the reason for Flash based vs. SRAM-based market %, but possibly a reason contributing to what others already said.

Although this is a bit late, this post makes a point a few others have noticed. The technology, SRAM or Flash, is utterly irrelevent to the speed of the array but does have an impact on Iq as RAM does need a bit more power than Flash. The reason is the flash cell is either on or off, but is only 1 transistor whereas RAM is several transistors (it take at least 6 to make a really low power RAM cell as these cells are static RAM). The reason this is irrelevent to the array is that these cells control a T gate or a MUX and have no other interaction with the logic. The memory is static. Only fuse based arrays are faster and these are not reprogrammable. The popularity of RAM based cells is based on maturity of technology and process (it's cheaper to make because it's what they started with) and has no reprogrammability limits. FerroRAM cells, which are Flash cells with a different gate insulator material that offers infinite reprogrammability, may replace both RAM and Flash in the future.

RAM based: Larger arrays with smaller and (sometimes) faster logic elements, infinite reprogrammability, ubiquity (almost any maker of RAM based FPGAs can be replaced by another, if not pin for pin), faster reprogrammabilty and cheaper.

Flash Based: Lower power, non-volatile and fewer parts.

Fuse Based: Lowest power, faster, higher density, but not reprogrammable.