main differences between CMOS and CMOS SOI Technology

soi technology

Hi All,

What are the main differences between the normal CMOS technology & the CMOS SOI technology (Silicon on insulator)?

Does it only affect the mos devices? i.e no change in the resistors, capacitors ...

Also for mos devices, what are the main differences between SOI mos & the normal mos from the layout perspective & from the performance perspective?

Regards,
Yassin

Re: SOI Technology

Depending on -which- SOI, it can be minor or major.

I work in fully depleted, 0.25 and 0.5um which gives
me zero bottom-plate source and drain capacitance
(making off device Cgg zero as well) and all devices
have no substrate leakage or parasitics.

I love FDSOI despite the device nonidealities, because
I don't have to worry about so many crappy aspects
that have nothing (good) to do with circuit performance.

Partially-depleted, you have the bottom-plate capacitances
back and implanted resistors now have bottom junctions,
body ties and voltcos. But you still have independent
well potentials for both flavors and at least the well
capacitance doesn't kill source followers etc. And PDSOI
if you respect the body-tie rules will give you the same
sort of DC linearity as JI.

In RF design the nonlinear junction capacitances of
PDSOI and JI can really limit RF linearity / distortion
at higher frequencies.