There are two types of Flat vs. Hierarchical maintenance: logical and physical.
Logical flattening (as mentioned above) is when the synthesis tool flattens the logical hierarchy into one module.
For physical flattening, think of a hard block delivered to an SOC. The hard block is designed separately and would deliver various models for the SOC to integrate it (verilog, LEF/DEF, SPEF, .lib etc). The hard block would be maintained as a separate hierarchy within the SOC. If you wish to flatten this hierarchy you would need to merge the hard block DEF and verilog into the SOC level resulting on one flattened DEF and verilog for the whole design. The advantage of flattening a design is for simplicity (especially if you have several levels of hierarchy you are dealing with) but the disadvantage is that now any change to the logic in what use to be the hard block, will now require you to take the whole design through the flow and you will now have a much larger runtime.