r2msrit
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Hello Everyone.
I am designing an RTL in verilog for LZSS Algorithm. I have a working code of for this algorithm in verilog. This code is pretty much written in C++ style in verilog. It runs and all looks good.
Now I want to increase the speed of this algorithm and I want to pipeline it . I have a detailed flowchart of this algorithm. Now looking at this flowchart Can I decide How many pipeline stages will this end up in. IS there a limitation of how much combinational logic I can do in a stage.
Please help me lay down a step by step process to get this flowchart to a pipelined verilog code.
Thanks in advance.
I am designing an RTL in verilog for LZSS Algorithm. I have a working code of for this algorithm in verilog. This code is pretty much written in C++ style in verilog. It runs and all looks good.
Now I want to increase the speed of this algorithm and I want to pipeline it . I have a detailed flowchart of this algorithm. Now looking at this flowchart Can I decide How many pipeline stages will this end up in. IS there a limitation of how much combinational logic I can do in a stage.
Please help me lay down a step by step process to get this flowchart to a pipelined verilog code.
Thanks in advance.