dw_man
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I am trying to run LVS using a design I created in Encounter but am receiving a number of errors. I have used the >saveNetlist -excludeLeafCells -includePowerGround command to create a netlist which includes VDD and VSS just like the layout.
My standard cells also include VBP and VBN pins which are not connected in the netlist. When I go into the netlist and edit the netlist and connect the VBP pins to VDD and VBN pins to VSS, the errors start to disappear. Is there a way for the tools to do this because it will take a lot of time to do this of every instance in the verilog netlist?
I tried this with a basic design of a couple of gates and with just VDD and VSS connected I was getting lots of mismatches. When I connected all the VBP and VBN to VDD and VSS, the LVS passed.
My standard cells also include VBP and VBN pins which are not connected in the netlist. When I go into the netlist and edit the netlist and connect the VBP pins to VDD and VBN pins to VSS, the errors start to disappear. Is there a way for the tools to do this because it will take a lot of time to do this of every instance in the verilog netlist?
I tried this with a basic design of a couple of gates and with just VDD and VSS connected I was getting lots of mismatches. When I connected all the VBP and VBN to VDD and VSS, the LVS passed.