lvs softchk contact

[mssong]

The extraction result shows softchk, but the comparison result is fine.

Can I ignore the softchk warning in this case?

Also, in the softchk database, there is an error “Check SOFTCHK nxwell CONTACT.”.

I think it might be due to guarding issue, so I attach the layout of psub, nwell guardring.

 

[sidun.av]

Hi @mssong
It's hard to guess if you do not attach the Calibre results screenshot and error markers on the layout...

Usually, Check SOFTCHK nxwell CONTACT is related to NWELL not connected to a power (VDD) potential. It might be intentional and might be an error, so the designer have to decide.

There are some suggestions/questions:
1. Did you clean your ERC check (and specified supply/ground names there)?
2. It looks like there is not enough space between PSUB GR and NWELL GR... Are you sure that they are not touching/overlapping?
3. What is the potential to which you connect your NWELLs?

P.S. I see that you have an array of transistors which is enclosed in a mesh-like guard ring structure. It is a terrible design approach in terms of 2nd order layout effects (LOD, WPE and so on) because each device will be subject to a stress from a guard ring. It is highly recommended to use a single guard ring for the entire array (it doesn't seem too big for me) and protect your array by surrounding it with dummy devices.

Hopefully, that helps.