Minh_Hoang_Le
Newbie
Dear all,
I am designing an Op Amp on 22 nm FDSOI process and having a problem on the layout of the PMOS pair.
I use the super-low vt tripple-well PMOS device for my PMOS pair (flip-well PMOS device). The pair is broken down into several sub-cells for layout matching pattern ABBAABBA. I have already built 3 guard-rings for the whole matching structure, which includes one inner PWGR connected to VDD, one middle DeepNWGR connected to VDD, and one outer SUBGR connected to VSS. However, when running LVS, calibre tool still says that my layout does not have the parasitic NW to psub junction diode. I think the outer SUBGR connected to VSS and the middle DeepNWGR connected to VDD should form this parasitic diode, but no at all.
Anyone has any idea on this problem?
Thank you!
I am designing an Op Amp on 22 nm FDSOI process and having a problem on the layout of the PMOS pair.
I use the super-low vt tripple-well PMOS device for my PMOS pair (flip-well PMOS device). The pair is broken down into several sub-cells for layout matching pattern ABBAABBA. I have already built 3 guard-rings for the whole matching structure, which includes one inner PWGR connected to VDD, one middle DeepNWGR connected to VDD, and one outer SUBGR connected to VSS. However, when running LVS, calibre tool still says that my layout does not have the parasitic NW to psub junction diode. I think the outer SUBGR connected to VSS and the middle DeepNWGR connected to VDD should form this parasitic diode, but no at all.
Anyone has any idea on this problem?
Thank you!
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