[SOLVED] LVS POC problem

[omar97]

Hello all,
I have a problem while designing IO pad ring.
I am using TSMC 65nm technology, I get alot of problems while checking LVS.
I decided to divide and debug problem.
I designed only IO ring without any STD cells.
Every thing is OK in LVS checking without any thing related to POC.
I get missing POC port, many nets that I guess they related to poc net, and many wrong nets.
In my IO cells there is only one pad related to POC which called PVDD2POC, this pad cell has only one inout port called VDDPST which is power of IO ring.

Anyone has experience on this technology can help me in this problem?

I am using ICC2 as layout design tool.
Calibre lvs as lvs verification tool.
Thanks.

 

[ThisIsNotSam]

You have to draw a label by hand on POC/VDD/VSS pads to help LVS recognize them.

 

[omar97]

You have to draw a label by hand on POC/VDD/VSS pads to help LVS recognize them.

Thanks for your reply.
I make something like that.
It gives me a short in text layer
Poc cell has only one port which name is fixed VDDPST.
Are you face something like this?

 

[ThisIsNotSam]

This is a common behavior with TSMC tech, it is well known. Imagine you had a ring with two VDDs. The IO cells cannot decide what they are and how they are named. So it becomes your job to draw labels on top of the pads to make a layout that is consistent with intended behavior.

 

[omar97]

This is a common behavior with TSMC tech, it is well known. Imagine you had a ring with two VDDs. The IO cells cannot decide what they are and how they are named. So it becomes your job to draw labels on top of the pads to make a layout that is consistent with intended behavior.

Thanks sir,
I will do that and I wish to be solved.
Your advice to me is to remove port name of poc cell which is VDDPST to POC, is that right?

 

[ThisIsNotSam]

No. You should ADD a label named POC to the POC cell.

 

[omar97]

No. You should ADD a label named POC to the POC cell.

Sir,
I told you that I don't have any ports in poc cell except only one port called VDDPST.
This port (VSSPST) which I hope to name it POC, I can't modify or connect any port except VDDPST port.
When I write in verilog connect POC port to this port (VDDPST), it gives me short on text layer, different names on one port.
I am actually spent more time debugging but I can't solve it.

 

[ThisIsNotSam]

You have to DRAW a label. Cannot be solved at RTL, obviously.

 

[omar97]

Thanks for your advice.
I draw a lable on calibredrv manually named POC, and port is successfully recognised.
Great thanks to you