LVS nets issue

[sleepy_shiba]

Hi ,

I have an internal avdd in my circuit, but even the layout is correct, the calibre lvs still show errors, as like my avdd is not connected to certain blocks.

I have done some experiments like : add a label of avdd, and here is the outcome.

and add the pin in schematic:

since after adding pins in schematic & layout will make LVS clean, I don't think the problem is my layout, does anyone know what might cause this issue?
any idea is appreciated!

Kalinda.

 

[dick_freebird]

You can have connectivity mismatches in a perfect layout if
the lower level blocks or top level pins are not completely
defined. Mask layer correctness is necessary but not sufficient.