love_analog
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I'm an analog guy trying to make sense of digital tools
a) once you APR a block through ICC, do you do a LVS on APR output. If so, how? for synthesis I know you do conformal or some equivalence checking, what do you do after Layout. do you compare the CEL format with Gate level netlist or RTL
b) Typ RTL has no power pins and I think the .syn will also not have power pins but the APR block will have power pins - how are they reconciled in LVS.
thanks
a) once you APR a block through ICC, do you do a LVS on APR output. If so, how? for synthesis I know you do conformal or some equivalence checking, what do you do after Layout. do you compare the CEL format with Gate level netlist or RTL
b) Typ RTL has no power pins and I think the .syn will also not have power pins but the APR block will have power pins - how are they reconciled in LVS.
thanks