[SOLVED] LVS failure in cadence for all layouts

Hi i did layout for many circuits in cadence and all seemed fine and passed LVS. I was able to run it many times. But recently wen i opened them all the layouts that once cleared the LVS is failing now. Netlists are failing to match. I closed everything and opened and tried again but still no luck. Can anyone pls tell me how to fix this?? Thank you!!!

Check your current switch- and stop- view-lists!

Thank you for the reply!!! checked switch and stop view list. In switch view list der is
"spectre cmos_sch cmos.sch schematic veriloga ahdl" and in stop view list der is "spectre".
Later after sometime i didn't change anything but all started matching again. But later to get pre and post layout simulation results i just added "extracted" word in switch view list. And now again all the other layouts are failing to match. But later when i remove the "extracted" word still i they are not matching. Can you pls tell What's the actual cause of this problem??? Thank you!!!!

Order matters, the first valid one will be taken. Check what
views your extraction is meant to work from. Also you
could be a bit more clear about how it fails, than "Doesn't
work, Waahhh!". Like did you get extracted netlists but
they mismatch, or failed to get netlists for one or the
other views, is the mismatch gross or specific, if specific
can you see that one of the views has a later date stamp
and possibly changed such that it -should- fail? Especially
if you are referencing libs that you do not own, and others
may touch....

Oh my apologies for not being specific about the error. I am able to obtain the netlists but they fail to match. The error is "The no of lines exceeded than specified by the variable lvsLimitLinesInOutFile". That is the only error i'm getting. I had this problem once before and i was suggested to change the default no of lines value from 20 to 1000. I tried that too but didn't work. Also previously when the netlists were matching i checked the no of lines and it was the default value 20 but then i didn't have any problem. Also could you pls let me know what "order matters, the first valid one will be taken" mean. I did just a single layout and i followed all the steps in order DRC, extract and LVS. Thank you for the help so far!!!

You have a plurality of view types in Cadence. Switch views are
the search-order in which hierarchy is traversed, until a stop
view (also taken in list order priority) is found.

As one example, if you have a "mature" design that already
has a layout view and an extracted view, and you go to do
another extraction, stop view list order:

layout extracted

will find the layout, choose it by list-order and extract the
connectivity.

extracted layout

will pick the extracted view and you try to extract the
extracted, but this likely fails because the view does
not contain layout "drawing" layers but "net" or whatever,
and none of the PCell features that are parsed for terminal
assignment and device recognition. You may get a null or
a malformed "extracted" view this time depending on
whether the extract script finds anything, or errors out.

Look at the extracted view as a layout and see if you
have anything resembling the source layout. Look at
the LVS input netlists for sane device callouts and
node assignments. What's busted?

Failing for line-count indicates a gross mismatch, like
a really munged extracted view. Inspect the extract
process log for better clues.