lvs errors like bad net connnection

Status
Not open for further replies.
M

monali P

Newbie level 3
Joined
Mar 16, 2015
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
16
Hello s
I have designed a schematic and layout of dual input dual output comparator. I have completed Dry run successfully. But facing errors in lvs run.
Screenshots of errors and layout is attached with it..
Plz help me with a solution.
These are the screen shots
 

Attachments

  • IMG-20150315-WA0023.jpg
    273.3 KB · Views: 118
  • IMG-20150315-WA0022.jpg
    280 KB · Views: 91
  • IMG-20150315-WA0021.jpg
    285.4 KB · Views: 84
  • IMG-20150315-WA0020.jpg
    501.9 KB · Views: 94
  • IMG-20150315-WA0018.jpg
    362.8 KB · Views: 100
Last edited by a moderator:

I think you have done matching for the bottom two NMOS current mirrors with different Pins like vss and gnd.
May be it causes the problem.

Try the both MOSes with same vss connection and do matching. May be you get cleared.
 

actually I have given Vss supply to nmos current mirrors of first two differential stages.
And gnd is given to latch output stage.
Will this cause problem?
 

Actually it is not a problem. But i think you matched those two transistors right?

If it is yes then bulk of these two devices must have same potential.

So it may cause the problem. So try to make it same gnd or vss then run and see the results.

thanks
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…