LVS error -> nrpop_dis_w

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omigaagimo

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I'm facing a really confusing problem!

I'm using old tsmc 0.18 (13d) cdb pdk in a new oa based!

I converted its data base with cadence cdb to oa and then manually reshaped techfile to solve a problem and after that everything gone right!

But when I run lvs it exits with this log


I searched the internet for solving this problem but I haven't found any!
Please don't ask me to use newer PDK release cuz as I found non of my university professors has used tsmc 0.18 libraries in newer cadence software! They say we use it for our newer PDK which are mostly 90nm based and for this reason we don't need that old PDK and we didn't get it!
I also didn't found the PDK any where else! Thus I must stick to this old version and try to solve its problem!!!

As it seems lvs has successfully finished its job but when it was going to show me some kind of POP up massage it failed!
 
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omigaagimo said:

1 0 9 "58 "nrpop_dis_w")
^
SYNTAX ERROR found at line 1 column 23 of file *string*
*Error* lineread/read: syntax error encountered in input
Click to expand...

Device lines should begin with a character (e.g. D for diode, M for MOSFET, R for resistor, X for subcircuits) plus a device number.
Try to find out where it lost this character. And make sure that quotation marks as well as brackets match.
 

erikl said:
Device lines should begin with a character (e.g. D for diode, M for MOSFET, R for resistor, X for subcircuits) plus a device number.
Try to find out where it lost this character. And make sure that quotation marks as well as brackets match.
Click to expand...

Dear erikl,

Thanks for your quick reply!
However I didn't catch what you mean by saying "where it lost this character. And make sure that quotation marks as well as brackets match"

I haven't done anything manually! I used virtuoso Layout GXL edition and used "Connectivity>Generate>from source" key and cadence generate and placed transistor on layout automatically from my schematic! I just done the routing as I didn't understand how I can configure its autorouter!!!

So how its possible that cadence droped a name? in addition where should I search for this error! I opend the folder which I sat on LVS menu for process file and I faced a lot of files! which one should be modified?

Thanks in advance for your consideration!
 

omigaagimo said:
So how its possible that cadence droped a name? in addition where should I search for this error! I opend the folder which I sat on LVS menu for process file and I faced a lot of files! which one should be modified?
Click to expand...

I really don't know. Seems your extracted layout netlist is corrupted. I'd just try and find the nrpop_dis_w device - it's a 2-terminal device - probably a resistor or a diode - between nodes 0 (GND) and 9 and change the line in the extracted netlist to
D1 0 9 "nrpop_dis_w" ; in case of a diode
... and see if the LVS (without extract!) succeeds, or another error appears. Or you totally delete this line in the netlist and try the LVS (without a new extraction) again.
 
Dear erikl,

I didn't find where you mentioned that I must search for that device!

But I found something interesting!
I opened lvs/extract.rul and found this!

Code: 
extractDevice("rppo1rpo_dis" prpop_dis_p plyx("PLUS") plyx("MINUS") poly_psub_via("B")
        spiceModel("rppo1rpo_dis")
        cellView("rphpoly_dis ivpcell")
        flagMalformed
)
   w = measureParameter(length (prpop_dis_p butting plyx) 0.5e-6)
   A = measureParameter(area (prpop_dis_p) 1e-12)
   l = calculateParameter(A/w)
   nameParameter(w "w" prpop_dis_p)
   nameParameter(l "l" prpop_dis_p)
   nameParameter( w "wSim" prpop_dis_p)
   nameParameter( l "lSim" prpop_dis_p)
   nameParameter( w "sumW" prpop_dis_p)
   nameParameter( l "sumL" prpop_dis_p)
   saveProperty( prpop_dis_p "model" "rppo1rpo_dis")

[COLOR="#FF0000"]nrpop_dis_p = geomAnd(nrpop_dis psub)
nrpop_dis_w = geomAnd(nrpop_dis nw_net)
extractDevice("rnpo1rpo_dis" nrpop_dis_w plyx("PLUS") plyx("MINUS") poly_nw_via("B")
        spiceModel("rnpo1rpo_dis")
        cellView("rnhpoly_dis ivpcell")
        flagMalformed
)
   w = measureParameter(length (nrpop_dis_w butting plyx) 0.5e-6)
   A = measureParameter(area (nrpop_dis_w) 1e-12)
   l = calculateParameter(A/w)
   nameParameter(w "w" nrpop_dis_w)
   nameParameter(l "l" nrpop_dis_w)
   nameParameter( w "wSim" nrpop_dis_w)
   nameParameter( l "lSim" nrpop_dis_w)
   nameParameter( w "sumW" nrpop_dis_w)
   nameParameter( l "sumL" nrpop_dis_w)
   saveProperty( nrpop_dis_w "model" "rnpo1rpo_dis")
[/COLOR]extractDevice("rnpo1rpo_dis" nrpop_dis_p plyx("PLUS") plyx("MINUS") poly_psub_via("B")
        spiceModel("rnpo1rpo_dis")
        cellView("rnhpoly_dis ivpcell")
        flagMalformed
)
   w = measureParameter(length (nrpop_dis_p butting plyx) 0.5e-6)
   A = measureParameter(area (nrpop_dis_p) 1e-12)
   l = calculateParameter(A/w)
   nameParameter(w "w" nrpop_dis_p)
   nameParameter(l "l" nrpop_dis_p)
   nameParameter( w "wSim" nrpop_dis_p)
   nameParameter( l "lSim" nrpop_dis_p)
   nameParameter( w "sumW" nrpop_dis_p)
   nameParameter( l "sumL" nrpop_dis_p)
   saveProperty( nrpop_dis_p "model" "rnpo1rpo_dis")


if( avSwitch("INCLUDE_DEVICES_WITHOUT_PCELLS") then switchProc2() )

extractCAP("M2" _capm2 CTM2("TOP") m2t56("BOT") spiceModel("mimcap")
    cellView("mimcap ivpcell tsmc18rf"))
   area_CAP = measureParameter(area (_capm2) 1e-12)
   pj_CAP = measureParameter(perimeter (_capm2) 1e-6)

Is there anything wrong with this file?
It seems this is a variable that must be assigned to some other extracted parasitics! But it's not defined as it must be defined!
I'm not a expert in developing skills! So i'm don't know how to fix this!
 
Last edited by a moderator:

Thats Funny!!!! Rather than funny!

It's really rediculous that this software randomely accept and reject my design! one time accept it and finishes its LVS one time not! I don't understand what's happening!

I really don't know how industries has relied for more than 2 decades on a software which randomly accept and reject designs! :|
 

omigaagimo said:
I don't understand what's happening!
Click to expand...
I don't understand this, either. At least not this random behaviour. Never come to know of.

omigaagimo said:
I really don't know how industries has relied for more than 2 decades on a software which randomly accept and reject designs! :|
Click to expand...

It's surely not the LVS software, this one has proved its reliability a million times. The lvs/extract.rul file probably is the problem: it has to be tailored for each new process, and so usually hasn't been checked for a long time and many cases.
"For thorough checking we have customers. They'll tell us if anything goes wrong."
Click to expand...
;-)
 
I faced another thing too!!!

At the begining of compare.rul, I saw this:
Code: 
; *****************************************************************
avCompareRules(
; groupModels(RES)
  ignoreParameterNormalization( t )
  mergeSplitGate( sameOrder )
  expandOnError((reduce t)(swap t)(swapThres t))
[COLOR="#FF0000"]  filter( "X" )[/COLOR]
  schematic( 
;   netlist( cdl "source.add" )
;   netlist( dfII "./myRun.vlr" )
    genericDevice( emptySubckt )
  )

When I ran LVS assura showed a warning and mention that I must change this filter command with filteroptions!
After doing that when I ran the LVS again assura changed its massage and said that it has ignored filterOptions( X )!!!

I surmise that may be the problem! compare rule is defined so to drop short elements! but assura won't accept this command and this leads to a curious problem of finding some element that must not be found!
 

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