lvs error: no power net present, different no. of ports

Fengwei said:

Hello.
I am suffering a lvs error.
I stream out the gds file from IC compiler.
Here, a part of the GDSOUTMAP is as follows.
--------------------------------------------------------------------------------------------------------------------
set_write_stream_options -map_layer ${GDSOUTMAP} -child_depth 99 \
-output_pin {text geometry} -output_design_intent
write_stream -format gds -lib_name ALUDFFSMALL -cells {ALUDFFSMALL} ALUDFFSMALL.str
--------------------------------------------------------------------------------------------------------------------
A 11[:20] 11 20
A 114[:1] 114 1
A 115[:1] 115 1
A 116[:10] 116 10
A 116[:1] 116 1
A 116[:16] 116 16
map----------------------------------------------------------------------------------------------------------------

However, calibre can't recognize the pin texts (only 3 pins can be recognized on left upper corner).
As a result, the power nets and ports are mismatched.
I tried to stream in Virtuoso, it seems like that there is no problem of the pin text.
What is the problem?
I appreciate any comments.

Best regards,
Fengwei

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