lvs error in hierarchical dsign

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vashistha

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I am working on the layout of instrumentation amplifier, my design is hierarchical i.e. there is three op amps in it. The layout of op amp is drc and lvs clean but when i instantiate the layout of op amp in the layout of instrumentation amplifier i got the lvs error.
Thanks
 
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Since the errors are related to Vdd and gnd nets, one mistake you may be doing is not shorting the vdd and gnd rails of individual opamp layouts. We can have only one Vdd and gnd rail in a layout. If such is the case then short them and do the LVS run.
 
Ya that was a problem, now i short the vdd and gnd rails of each op amp but still got the same error
 

When i simulate the file extracted from the layout i am getting the correct results but still getting the lvs error for vdd and gnd nets
 

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