yxo
Full Member level 4
- Joined
- Jul 13, 2007
- Messages
- 196
- Helped
- 26
- Reputation
- 52
- Reaction score
- 8
- Trophy points
- 1,298
- Location
- The Netherlands, Delft
- Activity points
- 2,303
yxo said:I placed ESD3DMY on core voltage MOS. I was confused because of some controdictions.
...
2. If I look into Layout Guidlines for Latch-up and I/O ESD I can read "unsilicided MOS is not allowed as the power-pin ESD protection device for thin oxide circuits".
yxo said:But if I combine ESD3DMY and RPO layers on 1V MOS I get an error during LVS
Use ESD3DMY to cover high voltage tolerant 3.3V NMOS I/O devices
No, it is for additional ESD protection.yxo said:Yes. When I place RPO only, everything is ok. As for diode, sorry, I didn't explain it clear. I meant that ASSURA finds out, detected (I saw it in the log file) and tried to extract it from layout . It is odd, because I think this diode only for simulation ...
It must have a layout view - otherwise it can't help for ESD protection javascript:emoticon('yxo said:... as it doesn't have layout view ...
That's why it is a rather big and powerful device for ESD protection javascript:emoticon('yxo said:... and its CV curve has megaamperes in forward bias(I found this diode in the tsmc library and made some simulation)
No, it is for additional ESD protection.yxo said:Yes. When I place RPO only, everything is ok. As for diode, sorry, I didn't explain it clear. I meant that ASSURA finds out, detected (I saw it in the log file) and tried to extract it from layout . It is odd, because I think this diode only for simulation ...
It must have a layout view - otherwise it can't help for ESD protection :-((yxo said:... as it doesn't have layout view ...
That's why it is a rather big and powerful device for ESD protection ;-)yxo said:... and its CV curve has megaamperes in forward bias(I found this diode in the tsmc library and made some simulation)
PostPosted: 04 Dec 2008 11:04 Post subject: Re: LVS error in ESD design
yxo wrote:
I placed ESD3DMY on core voltage MOS. I was confused because of some controdictions.
...
2. If I look into Layout Guidlines for Latch-up and I/O ESD I can read "unsilicided MOS is not allowed as the power-pin ESD protection device for thin oxide circuits".
erikl wrote:
AFAIR this is a typo. Should read: "silicided MOS is not allowed ..., because the high poly resistance is necessary for the protection.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?