lvs error for resistor

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vashistha

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I have to make a layout of 200k resistor so i connected 20 resistors in series,10k each. But when i done lvs it will give a property error.
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
1 0(1.055,0.705) r18 R
m: 1 m: ? (reduced instance)
Why so?
 

If it is an Assura error, check if You have switch sthing like SBAR_FEATURE. In some pdks resistors with multiple bars are "strangely" treated.
 

vashistha said:
i am using calibre
Click to expand...

Marking layer missing?

Perhaps the proper instructions for series (and parallel) resistors extraction and comparison are missing in your Calibre PEX/LVS rules' set? Check it!

Work-around:

1. use 20 series resistors in your schematic

or - if not enough space there -

2. create a sub-cell for these 20 series-connected resistors, i.e. a schematic, symbol and lvs symbol for it, and instance the symbol in the original schematic.
 

i am using unsalicided pplus resistor, it has three terminals (plus minus sub). How i make the sub terminal in layout.Is sub terminal connected to ground
 

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