LVS complaining about lower level hierarchal design

Hello,

I am at the chip level verification when the Assura LVS started to complain about mismatching in the lower level hierarchal design. To make it clear my highest chip-level design has four blocks connected together and to the PAD frame. The LVS complained about mismatching inside block1.



However, I never go to higher-level design without checking the LVS of the individual blocks and performing the post-layout simulation on the extracted view. So for me, I already passed successfully the LVS and parasitic extraction of the block 1 with no error, why the LVS is complaining about it in the next level?

Since I am sure and confident about my design blocks, I may need to have a type of LVS that will not propagate to the lower hierarchal. only check the top level, I am not sure if the called LVS black box.



Thank you in advance for your help

Best Regards

And once you instantiate it on the top level, you do not accidently short something inside the block by some accidental top-level metal?

What's the type of error you get?

You can tell assura to run certain levels flat rather than hierarchical. That might resovle issues like this.