LVS by ICC has VDD and VSS open Error

Hi, everybody.
I use IC compiler for P&R (TSMC65nmLP & std cell library). After route_zrt_auto, I check LVS by verify_lvs. VDD and VSS are open as follows.
** Total Floating ports are 0.
** Total Floating Nets are 0.
** Total SHORT Nets are 0.
ERROR : Logical Net VSS is open.
Node 264 is in the region ((0,113),(226,114)).
Node 362 is in the region ((0,109),(226,110)).
Node 7211 is in the region ((0,0),(226,121)).
Node 3786 is in the region ((0,59),(226,60)).
Node 7061 is in the region ((0,5),(226,6)).
Total seperated nodes are 5.
Potential connection region ((-1, 5), (227, 114)).
ERROR : Logical Net VDD is open.
Node 7209 is in the region ((0,0),(226,121)).
Node 170 is in the region ((0,114),(226,116)).
Node 2 is in the region ((0,118),(226,119)).
Node 3490 is in the region ((0,64),(226,66)).
Node 3614 is in the region ((0,60),(226,62)).
Node 6750 is in the region ((0,10),(226,12)).
Node 6864 is in the region ((0,6),(226,8)).
Total seperated nodes are 7.
Potential connection region ((-1, 7), (227, 119)).
** Total OPEN Nets are 2.
** Total Electrical Equivalent Error are 0.
** Total Must Joint Error are 0.

-- LVS END : --
Elapsed = 0:00:00, CPU = 0:00:00
Update error cell ...
1


However, I check pg connection by verify_pg_nets. There is no error.
Checking [VSS]:
There are no floating shapes
All the pins are connected.
No errors are found.
Checking [VDD]:
There are no floating shapes
All the pins are connected.
No errors are found.
Checked 2 nets, 0 have Errors
Update error cell ...
1
The following is the result by check_mv_design:
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Clock Gating Style Checks
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No clock gating style defined yet.

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Target Library Subset Checks
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No Errors/Warnings Found.

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Power Domain Checks
--------------------------------------------------------------------------------

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Cell Operating Condition Checks
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No Errors/Warnings Found.

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Power Domain and Operating Condition Consistency Checks
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No Errors/Warnings Found.
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Power/Ground Pin Connection Checks
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Power/Ground Connection Summary:

P/G net name P/G pin count
--------------------------------------------------------------------
Other power nets: 27862
Unconnected power pins: 0

Other ground nets: 27862
Unconnected ground pins: 0
--------------------------------------------------------------------
Warning: Auto derivation of P/G nets for 13886 P/G pins failed. (MV-598)

--------------------------------------------------------------------------------
Supply Operating Voltage Checks
--------------------------------------------------------------------------------
No Errors/Warnings Found.

Please review report above for warnings and errors.
1

What is the problem? Please help me to solve this problem.

solved by remove the strap

I am having similiar issues , could you please elaborate how/why you did this ?

Fengwei said:

solved by remove the strap

Click to expand...

Aren't the power straps needed?

Need help.