LVDS, relation berween signal level and data rate

[AdvaRes]

LVDS

Hi members,
I found this information is an application note from National semiconductor:

To achieve high data rate, low power and to reduce EMl effects,
signaling levels have to be reduced.

**broken link removed**

Could someone explain for me how reducing signals level acheves high data rates ? Is there a relation between signal level and data rate ?

Thanks.

 

[abcyin]

LVDS

I think that's because if you decrease the signal level, the slope of the rise edge and fall edge can be decreased, thus slew rate performance could be relaxed, that seems the reason, it's my opinion, rectify if there is something wrong.
THx.

 

[FvM]

Re: LVDS

Is there a relation between signal level and data rate ?

Strictly speaking it isn't, I think. Usual high speed I/O standards have different voltage swings between 300 and 800 mV. Of course there is a minimum voltage level in terms of signal to noise ratio and noise bandwidth. Cause thermal noise at GHz bandwidth is in the mV range, you have sufficient margin even for above GBit standards. High speed standards are generally using impedance matching, with 50 or 100 ohms there is also a natural level limitation set by the power consumption and available small signal driver transistors.