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I am working on a LVDS driver to send some digital data from an ASIC to an FPGA with a relatively high speed (min 500 Mbps) and a cable of undefined length (ideally 1 meter long, but depends on what I manage to do within the time I have).

A simple testbench with the termination resistor was looking good, and I wanted to simulate a different (better? maybe) model, so I thought about adding a transmission line to add the contribution of the cable.

As I mentioned, I haven't got definitive specifications for the cables etc, it's more an explorative design to see where I can get, and my question was more about the setup of the testbench than actual values.

For reference, I set the characteristic impedance of the tlines at 50 Ohm and the delay parameter at 6 ns, which seems compatible with 1 meter long Cat5 cable.

If you have more hints and do's and don'ts I'm very happy to know more!

Thank you