LVDS Driver Simulation

[SteS]

Hello everyone,
I am working on a LVDS driver. I am using Virtuoso and Spectre simulator. The architecture is pretty standard and is shown in the following image.
The top current sources are controlled by an active high digital signal and provide about 4 mA. The Rcm resistors are large for common mode estimation. The CMFB amplifier has modest gain and high bandwidth (is this correct? Even if the common mode is not precisely set at 1.25 V, it should stay into the LVDS specifications).

My first testbench is a simple 100 Ohm termination resistor connected between Vop and Von all the analysis (DC, stb and tran) seem to give good results. An iprobe component is inserted between the output of the amplifier and the Vcmfb node, to get the behavior of the CMFB loop. The DC point is the expected one, the CMFB loop has a large phase margin and the digital outputs look correct.

I want to make a more accurate simulation by inserting a transmission line, but I am unsure of the correct way to use the component. I would like to use mtline, since they say tline is deprecated and mtline is overall better. My only cable parameters are a characteristic impedance of 50 Ohm and a delay of 6 ns, these should be enough to characterize it with the mtline component if the "tline" type of input is selected.

Is this the correct way to use it? I tried to select 2 wires in a single mtline component but I get an error (ERROR (CMI-2515): I16: Incorrect number of terminals for mtline using tline parameters.) so I guess only a single wire configuration can be used with the "tline" type of input.
The stb analisys gives this Bode plot, which I did not expect, and in the tran simulation the two Vop and Von outputs get progressively worse, probably because of reflected waves (because the interactions between voltage before and after the tline can be seen).

So my questions are:
- is my use of the mtline component correct?
- can you confirm that the Bode plot can look like that and it is not a simulation artifact or caused by a wrong testbench?
- is the bad tran behavior due to incorrect impedance matching?

Thank you

 

[dick_freebird]

You can't get a "more accurate simulation" by adding a transmission line model of unknown "accuracy" - accuracy involving both a projectile and a target, what is an actual application target (thence, model)?

 

[SteS]

I am working on a LVDS driver to send some digital data from an ASIC to an FPGA with a relatively high speed (min 500 Mbps) and a cable of undefined length (ideally 1 meter long, but depends on what I manage to do within the time I have).

A simple testbench with the termination resistor was looking good, and I wanted to simulate a different (better? maybe) model, so I thought about adding a transmission line to add the contribution of the cable.
As I mentioned, I haven't got definitive specifications for the cables etc, it's more an explorative design to see where I can get, and my question was more about the setup of the testbench than actual values.

For reference, I set the characteristic impedance of the tlines at 50 Ohm and the delay parameter at 6 ns, which seems compatible with 1 meter long Cat5 cable.

If you have more hints and do's and don'ts I'm very happy to know more!

Thank you